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micr on parallel nor flash embedded memory (p30-65nm) js28f512p30bfx, js28f512p30efx, js28f512p30tfx, pc28f512p30bfx, pc28f512p30efx, pc28f512p30tfx js28f00ap30bfx, js28f00ap30tfx, js28f00ap30efx, pc28f00ap30bfx, pc28f00ap30tfx, pc28f00ap30efx, rc28f00ap30bfx, rc28f00ap30tfx, pc28f00bp30efx featur es ? h igh per for mance ? easy bga package featur es C 100ns initial access for 512mb , 1gb easy bga C 105ns initial access for 2gb easy bga C 25ns 16-wor d asy chr onous page r ead mode C 52 mhz (easy bga) with z er o w ait states and 17ns clock-to-data output synchr onous burst r ead mode C 4-, 8-, 16-, and continuous wor d options for burst mode ? t sop package featur es C 110ns initial access for 512mb , 1gb t sop ? b oth easy bga and t sop package featur es C b uffer ed enhanced factor y pr ogr amming (befp) at 2 mb/s ( t yp) using a 512-wor d buffer C 1.8v buffer ed pr ogr amming at 1.46 mb/s ( t yp) using a 512-wor d buffer ? ar chitectur e C ml c: highest density at lo w est cost C s ymmetr ically blocked ar chitectur e (512mb , 1gb , 2gb) C asymmetr ically blocked ar chitectur e (512mb , 1gb); four 32kb par ameter blocks: top or bottom configur ation C 128kb main blocks C b lank check to v er ify an er ased block ? v oltage and po w er C v c c (cor e) v oltage: 1.7C2.0v C v c c q (i/o) v oltage: 1.7C3.6v C s tandy curr ent: 70a ( t yp) for 512mb; 75a ( t yp) for 1gb C 52 mhz continuous synchr onous r ead curr ent: 21ma ( t yp), 24ma (ma x) ? s ecur ity C o ne-time pr ogr ammable r egister : 64 o tp bits , pr ogr ammed with unique infor mation fr om m i- cr on; 2112 o tp bits av ailable for customer pr o- gr amming C a bsolute wr ite pr otection: v pp = v ss C p o w er -tr ansition er ase/pr ogr am lockout C i ndividual z er o-latency block locking C i ndividual block lock-do wn C p asswor d access ? s oftwar e C 25 s ( t yp) pr ogr am suspend C 25 s ( t yp) er ase suspend C f lash d ata i ntegr ator optimiz ed C b asic command set and extended function i nter - face (efi) command set compatible C c ommon flash inter face ? d ensity and p ackaging C 56-lead t sop package (512mb , 1gb) C 64-ball easy bga package (512mb , 1gb , 2gb) C 16-bit wide data bus ? q uality and r eliabilty C jesd47 compliant C o per ating temper atur e: C40c to +85c C minimum 100,000 erase cycles per block C 65nm process technology 512mb, 1gb, 2gb: p30-65nm features pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 1 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron t echnology , inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice. http://
discr ete and mcp part numbering information d evices ar e shipped fr om the factor y with memor y content bits er ased to 1. f or av ailable options , such as pack- ages or for fur ther infor mation, contact y our m icr on sales r epr esentativ e . p ar t numbers can be v er ified at www .mi- cr on.com . f eatur e and specification compar ison b y device type is av ailable at www .micr on.com/pr oducts . c on- tact the factor y for devices not found. note: not all part numbers listed here are available for ordering. table 1: discrete part number information part number category category details package js = 56-lead tsop, lead free pc = 64-ball easy bga, lead-free rc = 64-ball easy bga, leaded product line 28f = micron flash memory density 512 = 512mb 00a = 1gb 00b = 2gb product family p30 (v cc = 1.7C2.0v; v ccq = 1.7C3.6v) parameter location b/t = bottom/top parameter e = symmetrical blocks lithography f = 65nm features * note: 1. the last digit is assigned randomly to cover packaging media, features, or other specific configuration infor- mation. sample part number: js28f512p30ef* table 2: standard part numbers density configuration medium js pc rc 512mb bottom boot tray js28f512p30bfa pc28f512p30bfa C tape & reel C pc28f512p30bfb C top boot tray js28f512p30tfa pc28f512p30tfa C tape & reel C pc28f512p30tfb C uniform tray js28f512p30efa pc28f512p30efa C tape & reel C C C 1gb bottom boot tray js28f00ap30bfa pc28f00ap30bfa rc28f00ap30bfa tape & reel C pc28f00ap30bfb C top boot tray JS28F00AP30BTFA pc28f00ap30tfa rc28f00ap30tfa tape & reel C C C uniform tray js28f00ap30efa pc28f00ap30efa C tape & reel C C C 2gb uniform tray C pc28f00bp33efa C tape & reel C C C 512mb, 1gb, 2gb: p30-65nm features pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 2 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
contents g ener al d escr iption ......................................................................................................................................... 7 v ir tual chip e nable d escr iption ........................................................................................................................ 8 m emor y m ap ................................................................................................................................................... 9 p ackage d imensions ....................................................................................................................................... 11 pinouts and b allouts ....................................................................................................................................... 13 s ignal d escr iptions ......................................................................................................................................... 15 b us o per ations ............................................................................................................................................... 17 r ead .......................................................................................................................................................... 17 w r ite .......................................................................................................................................................... 17 o utput d isable ........................................................................................................................................... 17 s tandb y ..................................................................................................................................................... 17 r eset .......................................................................................................................................................... 18 d evice c ommand c odes ................................................................................................................................. 19 d evice c ommand b us c y cles .......................................................................................................................... 22 r ead o per ations ............................................................................................................................................. 24 asynchr onous s ingle w or d r ead ..................................................................................................................... 24 asynchr onous p age m ode r ead (easy bga o nly) ............................................................................................. 24 s ynchr onous b urst m ode r ead (easy bga o nly) .............................................................................................. 25 r ead cfi ........................................................................................................................................................ 25 r ead d evice id ............................................................................................................................................... 25 d evice id c odes ............................................................................................................................................. 26 p r ogr am o per ations ....................................................................................................................................... 27 w or d p r ogr amming (40h) ........................................................................................................................... 27 b uffer ed p r ogr amming (e8h, d0h) .............................................................................................................. 27 b uffer ed e nhanced f actor y p r ogr amming (80h, d0h) ................................................................................... 28 p r ogr am s uspend ....................................................................................................................................... 30 p r ogr am r esume ........................................................................................................................................ 31 p r ogr am p r otection .................................................................................................................................... 31 e r ase o per ations ............................................................................................................................................ 32 bl ock erase c ommand ........................................................................................................................... 32 bl ank check c ommand .......................................................................................................................... 32 erase susp end c ommand ....................................................................................................................... 33 erase resume c ommand ........................................................................................................................ 33 e r ase p r otection ......................................................................................................................................... 33 s ecur ity o per ations ........................................................................................................................................ 34 b lock locking ............................................................................................................................................. 34 bl ock l ock c ommand ............................................................................................................................ 34 bl ock unl ock c ommand ....................................................................................................................... 34 bl ock l ock do wn c ommand ................................................................................................................. 34 b lock lock s tatus ....................................................................................................................................... 34 b lock locking d ur ing s uspend ................................................................................................................... 35 s electable o tp b locks ................................................................................................................................. 36 p asswor d a ccess ......................................................................................................................................... 36 s tatus r egister ................................................................................................................................................ 37 r ead s tatus r egister ................................................................................................................................... 37 clear s tatus r egister ................................................................................................................................... 38 c onfigur ation r egister .................................................................................................................................... 39 r ead c onfigur ation r egister ....................................................................................................................... 39 r ead m ode ................................................................................................................................................. 39 latency count ............................................................................................................................................ 40 512mb, 1gb, 2gb: p30-65nm features pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 3 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
e nd of w or dline c onsider ations .................................................................................................................. 41 w ait s ignal p olar ity and f unctionality ........................................................................................................ 42 w ait d elay ................................................................................................................................................ 43 b urst s equence .......................................................................................................................................... 43 clock e dge ................................................................................................................................................. 44 b urst w r ap ................................................................................................................................................. 44 b urst length .............................................................................................................................................. 44 o ne-t ime p r ogr ammable r egisters ................................................................................................................. 45 r ead o tp r egisters ..................................................................................................................................... 45 p r ogr am o tp r egisters ............................................................................................................................... 46 lock o tp r egisters ..................................................................................................................................... 46 c ommon f lash i nter face ................................................................................................................................ 48 read cfi s tr uctur e o utput ........................................................................................................................ 48 f lo w char ts ..................................................................................................................................................... 62 p o w er and r eset s pecifications ....................................................................................................................... 71 p o w er s upply d ecoupling ........................................................................................................................... 72 m aximum r atings and o per ating c onditions .................................................................................................. 73 dc e lectr ical s pecifications ............................................................................................................................ 74 a c t est c onditions and c apacitance ............................................................................................................... 76 a c r ead s pecifications ................................................................................................................................... 78 a c w r ite s pecifications ................................................................................................................................... 85 p r ogr am and e r ase char acter istics .................................................................................................................. 91 r evision h istor y ............................................................................................................................................. 92 r ev . b C 12/13 ............................................................................................................................................. 92 rev. a C 8/13 ............................................................................................................................................... 92 512mb, 1gb, 2gb: p30-65nm features pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 4 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of figur es f igur e 1: easy bga b lock d iagr am ................................................................................................................... 8 f igur e 2: m emor y m ap C 512mb and 1gb ......................................................................................................... 9 f igur e 3: m emor y m ap C 2gb ......................................................................................................................... 10 f igur e 4: 56-pin t sop C 14mm x 20mm .......................................................................................................... 11 f igur e 5: 64-b all easy bga C 8mm x 10mm x 1.2mm ....................................................................................... 12 f igur e 6: 56-lead t sop pinout C 512mb and 1gb ........................................................................................... 13 f igur e 7: 64-b all easy bga ( t op v iew C b alls do wn) C 512mb , 1gb , and 2gb .................................................... 14 f igur e 8: e xample v pp s upply c onnections .................................................................................................... 31 f igur e 9: b lock locking s tate d iagr am ........................................................................................................... 35 f igur e 10: f irst a ccess latency c ount ............................................................................................................ 40 f igur e 11: e xample latency c ount s etting u sing c ode 3 ................................................................................. 41 f igur e 12: e nd of w or dline t iming d iagr am ................................................................................................... 41 f igur e 13: o tp r egister m ap .......................................................................................................................... 46 f igur e 14: w or d p r ogr am p r ocedur e ............................................................................................................... 62 f igur e 15: b uffer p r ogr am p r ocedur e .............................................................................................................. 63 f igur e 16: b uffer ed e nhanced f actor y p r ogr amming (befp) p r ocedur e ........................................................... 64 f igur e 17: b lock e r ase p r ocedur e ................................................................................................................... 65 f igur e 18: p r ogr am s uspend/r esume p r ocedur e ............................................................................................ 66 f igur e 19: e r ase s uspend/r esume p r ocedur e ................................................................................................. 67 f igur e 20: b lock lock o per ations p r ocedur e ................................................................................................... 68 f igur e 21: o tp r egister p r ogr amming p r ocedur e ............................................................................................ 69 f igur e 22: s tatus r egister p r ocedur e .............................................................................................................. 70 f igur e 23: r eset o per ation w av efor ms ........................................................................................................... 72 f igur e 24: a c i nput/o utput r efer ence t iming ................................................................................................ 76 f igur e 25: t r ansient e quiv alent load cir cuit .................................................................................................. 76 f igur e 26: clock i nput a c w av efor m .............................................................................................................. 76 f igur e 27: asynchr onous s ingle-w or d r ead (ad v# l o w ) ................................................................................ 80 f igur e 28: asynchr onous s ingle-w or d r ead (ad v# latch) ............................................................................... 80 f igur e 29: asynchr onous p age m ode r ead ...................................................................................................... 81 f igur e 30: s ynchr onous s ingle-w or d arr ay or n onarr ay r ead .......................................................................... 82 f igur e 31: c ontinuous b urst r ead with o utput d elay ..................................................................................... 83 f igur e 32: s ynchr onous b urst m ode 4-w or d r ead ........................................................................................... 84 f igur e 33: w r ite to w r ite t iming .................................................................................................................... 87 f igur e 34: asynchr onous r ead to w r ite t iming ............................................................................................... 87 f igur e 35: w r ite to asynchr onous r ead t iming ............................................................................................... 88 f igur e 36: s ynchr onous r ead to w r ite t iming ................................................................................................ 89 figure 37: write to synchronous read timing ................................................................................................ 90 512mb, 1gb, 2gb: p30-65nm features pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 5 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of t ables t able 1: d iscr ete p ar t n umber i nfor mation ...................................................................................................... 2 t able 2: s tandar d p ar t n umbers ....................................................................................................................... 2 t able 3: v ir tual chip e nable t r uth t able for easy bga p ackages ........................................................................ 8 t able 4: t sop and easy bga s ignal d escr iptions ............................................................................................ 15 t able 5: b us o per ations ................................................................................................................................. 17 t able 6: c ommand c odes and d efinitions ...................................................................................................... 19 t able 7: c ommand b us c y cles ....................................................................................................................... 22 t able 8: d evice id i nfor mation ...................................................................................................................... 25 t able 9: d evice id codes ................................................................................................................................ 26 t able 10: befp r equir ements ........................................................................................................................ 29 t able 11: befp c onsider ations ...................................................................................................................... 29 t able 12: s tatus r egister d escr iption .............................................................................................................. 37 t able 13: r ead c onfigur ation r egister ............................................................................................................ 39 t able 14: e nd of w or dline d ata and w ait s tate c ompar ison ........................................................................... 42 t able 15: w ait f unctionality t able ................................................................................................................ 42 t able 16: b urst s equence w or d or der ing ........................................................................................................ 43 t able 17: e xample of cfi o utput (x16 device) as a f unction of d evice and m ode ............................................. 48 t able 18: cfi d atabase: a ddr esses and s ections ............................................................................................. 49 t able 19: cfi id s tr ing ................................................................................................................................... 49 t able 20: s ystem i nter face i nfor mation .......................................................................................................... 50 t able 21: d evice g eometr y ............................................................................................................................ 51 t able 22: b lock r egion m ap i nfor mation ........................................................................................................ 51 t able 23: p r imar y v endor -s pecific e xtended q uer y ........................................................................................ 52 t able 24: o ptional f eatur es f ield ................................................................................................................... 54 t able 25: o ne t ime p r ogr ammable (o tp) s pace i nfor mation .......................................................................... 54 t able 26: b urst r ead i nfor mation ................................................................................................................... 55 t able 27: p ar tition and b lock e r ase r egion i nfor mation .................................................................................. 56 t able 28: p ar tition r egion 1 i nfor mation: t op and b ottom offset/a ddr ess ....................................................... 57 t able 29: p ar tition r egion 1 i nfor mation ........................................................................................................ 57 t able 30: p ar tition r egion 1: p ar tition and e r ase b lock m ap i nfor mation ......................................................... 60 t able 31: cfi link i nfor mation C 2gb ............................................................................................................. 61 t able 32: p o w er and r eset .............................................................................................................................. 71 t able 33: m aximum r atings ........................................................................................................................... 73 t able 34: o per ating c onditions ...................................................................................................................... 73 t able 35: dc c urr ent char acter istics .............................................................................................................. 74 t able 36: dc v oltage char acter istics .............................................................................................................. 75 t able 37: t est c onfigur ation: w orst-c ase s peed c ondition .............................................................................. 76 t able 38: c apacitance .................................................................................................................................... 77 t able 39: a c r ead s pecifications .................................................................................................................... 78 t able 40: a c w r ite s pecifications ................................................................................................................... 85 table 41: program and erase specifications .................................................................................................... 91 512mb, 1gb, 2gb: p30-65nm features pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 6 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
general description the m icr on p ar allel nor f lash memor y is the latest gener ation of f lash memor y devi- ces . b enefits include mor e density in less space , high-speed inter face device , and sup- por t for code and data stor age . f eatur es include high-per for mance synchr onous-burst r ead mode , fast asynchr onous access times , lo w po w er , flexible secur ity options , and thr ee industr y -standar d package choices . the pr oduct family is manufactur ed using m i- cr on 65nm pr ocess technology . the nor f lash device pr o vides high per for mance at lo w v oltage on a 16-bit data bus . i ndividually er asable memor y blocks ar e siz ed for optimum code and data stor age . u pon initial po w er up or r etur n fr om r eset, the device defaults to asynchr onous page- mode r ead. c onfigur ing the r ead configur ation r egister enables synchr onous burst- mode r eads . i n synchr onous burst mode , output data is synchr oniz ed with a user -sup- plied clock signal. a w ait signal pr o vides easy cpu-to-flash memor y synchr onization. i n addition to the enhanced ar chitectur e and inter face , the device incorpor ates technol- ogy that enables fast factor y pr ogram and erase oper ations . d esigned for lo w-v olt- age systems , the devi ce suppor ts read oper ations with v c c at the lo w v oltages , and erase and pr ogram oper ations with v pp at the lo w v oltages or v pp h . b uffer ed en- hanced factor y pr ogr amming (befp) pr o vides the fastest f lash arr ay pr ogr amming per - for mance with v pp at v pp h , which incr eases factor y thr oughput. w ith v pp at lo w v oltag- es , v c c and v pp can be tied together for a simple , ultr a lo w-po w er design. i n addition to v oltage flexibility , a dedicated v pp connection pr o vides complete data pr otection when v pp v pplk . a command user inter face is the inter face betw een the system pr ocessor and all inter - nal oper ations of the device . the device automatically executes the algor ithms and tim- ings necessar y for block er ase and pr ogr am. a status r egister indicates erase or pr o- gram completion and any err ors that may hav e occurr ed. an industr y -standar d command sequence inv okes pr ogr am and er ase automation. each erase oper ation er ases one block. the er ase suspend featur e enables system soft- war e to pause an erase cy cle to r ead or pr ogr am data in another block. p r ogr am sus- pend enables system softwar e to pause pr ogr amming to r ead other locations . d ata is pr ogr ammed in wor d incr ements (16 bits). the pr otection r egister enables unique device identification that can be used to in- cr ease system secur ity . the individual block lock featur e pr o vides z er o-latency block locking and unlocking. the device includes enhanced pr otection via passwor d access; this new feature supports write and/or read access protection of user-defined blocks. in addition, the device also provides the full-device otp security feature. 512mb, 1gb, 2gb: p30-65nm general description pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 7 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
v irtual chip enable description the 2gb device emplo ys a vir tual chip enable featur e , which combines two 1gb die with a common chip enable , ce# for easy bga packages . the maximum addr ess bit is then used to select between the die pair with ce# asserted. when ce# is asserted and the maximum address bit is low, the lower parameter die is selected; when ce# is as- serted and the maximum address bit is high, the upper parameter die is selected. table 3: virtual chip enable truth table for easy bga packages die selected ce# a[max] lower parameter die l l upper parameter die l h figur e 1: easy bga block diagram parameter configuration easy bga (dual die) top/bottom bottom parameter die top parameter die ce# a[max:1] adv# clk we# oe# wp# wait dq[15:0] rst# v pp v ccq v cc v ss 512mb, 1gb, 2gb: p30-65nm virtual chip enable description pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 8 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
memory map figur e 2: memory map C 512mb and 1gb bottom boot 512mb and 1gb, world-wide x16 mode a[25:1] 512mb and a[26:1] 1gb 3ff0000 - 3ffffff 1ff0000 - 1ffffff ff0000 - ffffff 000000 - 003fff 004000 - 007fff 008000 - 00bfff 00c000 - 00ffff 010000 - 01ffff 020000 - 02ffff 16 kword block 0 16 kword block 1 16 kword block 2 16 kword block 3 64 kword block 4 64 kword block 5 64 kword block 514 64 kword block 1026 64 kword block 258 1gb 512mb symetrically blocked 512mb and 1gb, world-wide x16 mode 3ff0000 - 3ffffff 1ff0000 - 1ffffff ff0000 - ffffff 000000 - 00ffff 010000 - 01ffff 020000 - 02ffff 030000 - 03ffff 64 kword block 0 64 kword block 1 64 kword block 2 64 kword block 3 64 kword block 511 64 kword block 1023 64 kword block 255 1gb 512mb 000000 - 00ffff 010000 - 01ffff 64 kword block 0 64 kword block 1 1ff0000 - 1ff3fff 1ff4000 - 1ff7fff 1ff8000 - 1ffbfff 1ffc000 - 1ffffff 1fe0000 - 1feffff 16 kword block 511 16 kword block 512 16 kword block 513 16 kword block 514 64 kword block 510 top boot 512mb, world wide x16 mode 512mb 000000 - 00ffff 010000 - 01ffff 64 kword block 0 64 kword block 1 3ff0000 - 3ff3fff 3ff4000 - 3ff7fff 3ff8000 - 3ffbfff 3ffc000 - 3ffffff 3fe0000 - 3feffff 16 kword block 1023 16 kword block 1024 16 kword block 1025 16 kword block 1026 64 kword block 1022 top boot 1gb, world wide x16 mode 1gb 512mb, 1gb, 2gb: p30-65nm memory map pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 9 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 3: memory map C 2gb a[27:1] 2gb (1gb/1gb) world-wide x16 mode 000000 - 00ffff 010000 - 01ffff 020000 - 02ffff 64 kword block 0 64 kword block 1 64 kword block 2 3ff0000 - 3ffffff 4000000 - 400ffff 4011000 - 401ffff 64 kword block 1023 64 kword block 1024 64 kword block 1025 7ff0000 - 7ffffff 64 kword block 2047 1ff0000 - 1ffffff ff0000 - ffffff 64 kword block 511 64 kword block 255 1gb 2gb 512mb 512mb, 1gb, 2gb: p30-65nm memory map pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 10 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
package dimensions figur e 4: 56-pin tsop C 14mm x 20mm see detail a 0.5 typ 14.00 0.2 0.25 0.1 1.20 max 18.4 0.2 0.995 0.03 20 0.2 0.22 0.05 detail a 0.60 0.10 0.05 min 0.10 seating plane pin #1 index see notes 2 see note 2 see note 2 see note 2 0.15 0.05 3 +2 -3 notes: 1. all dimensions are in millimeters. drawing not to scale. 2. one dimple on package denotes pin 1; if two dimples, then the larger dimple denotes pin 1. pin 1 will always be in the upper left corner of the package, in reference to the product mark. 3. for the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 512mb, 1gb, 2gb: p30-65nm package dimensions pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 11 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 5: 64-ball easy bga C 8mm x 10mm x 1.2mm ball a1 id 0.78 typ 0.25 min seating plane 0.1 1.20 max 1.00 typ a b c d e f g h 8 7 6 5 4 3 2 1 0.5 0.1 10 0.1 64x ?0.43 0.1 1.00 typ 8 0.1 1.5 0.1 ball a1 id notes: 1. all dimensions are in millimeters. drawing not to scale. 2. the 512mb device does not contain the a1 id ball located on the back side of the de- vice. 512mb, 1gb, 2gb: p30-65nm package dimensions pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 12 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
pinouts and ballouts figur e 6: 56-lead tsop pinout C 512mb and 1gb 56-lead tsop pinout 14mm x 20mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a 14 a 13 a 12 a 10 a 9 a 11 vss a 23 a 21 a 22 rfu wp # a 20 we # a 19 a 8 a 7 a 18 a 6 a 4 a 3 a 5 a 2 a25 a26 a24 wait dq 15 dq 7 a 17 dq 14 dq 13 dq 5 dq 6 dq 12 adv # clk dq 4 rst # a 16 dq 3 vpp dq 10 vccq dq 9 dq 2 dq 1 dq 0 vcc dq 8 oe # ce # a 1 vss a 15 dq 11 notes: 1. a1 is the least significant address bit. 2. adv# must be tied to v ss or driven to low throughout the asynchronous read mode. 3. a25 is valid for 512mb densities and above; otherwise, it is a no connect (nc). 4. a26 is valid for 1gb densities and above; otherwise, it is a no connect (nc). 5. one dimple on package denotes pin 1 which will always be in the upper left corner of the package, in reference to the product mark. 512mb, 1gb, 2gb: p30-65nm pinouts and ballouts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 13 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 7: 64-ball easy bga (t op v iew C balls down) C 512mb, 1gb, and 2gb a b c d e f g h 1 a1 a2 rfu rfu dq8 a23 a24 a27 2 a6 a4 a14 a7 a3 a5 dq1 dq0 ce# rfu v ss v ss 3 a8 a17 a10 a11 dq9 dq10 dq2 4 v pp wp# a12 rst# dq3 dq11 5 we# a15 a19 dq4 dq12 v cc v ccq v ccq v cc v ccq dq13 6 a9 clk adv# dq6 dq14 dq7 dq5 7 a18 a22 a20 a16 a25 dq15 wait v ss 8 a26 a21 v ss oe# a13 notes: 1. a1 is the least significant address bit. 2. a25 is valid for 512mb densities and above; otherwise, it is a no connect (nc). 3. a26 is valid for 1gb densities and above; otherwise, it is a no connect (nc). 4. a27 is valid for 2gb densities and above; otherwise, it is a no connect (nc). 5. one dimple on package denotes pin 1 which will always be in the upper left corner of the package, in reference to the product mark. 512mb, 1gb, 2gb: p30-65nm pinouts and ballouts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 14 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal descriptions table 4: tsop and easy bga signal descriptions symbol type name and function a[max:1] input addr ess inputs: device address inputs. note: unused active address pins should not be left floating; tie them to v ccq or v ss ac- cording to specific design requirements. adv# input addr ess valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low , which- ever occurs first. in asynchronous mode, the address is latched when adv# goes high or continuously flows through if adv# is held low . note: designs not using adv# must tie it to v ss to allow addresses to flow through. ce# input chip enable: active low input. ce# low selects the associated die. when asserted, inter - nal control logic, input buf fers, decoders, and sense amplifiers are active. when de-asser - ted, the associated die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z. note: ce# must be driven high when device is not in use. clk input clock: synchronizes the device with the system bus frequency in synchronous-read mode. during synchronous reads, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low , whichever occurs first. note: designs not using clk for synchronous read mode must tie it to v ccq or v ss . oe# input output enable: active low input. oe# low enables the devices output data buf fers during read cycles. oe# high places the data outputs and wait in high-z. rst# input reset: active low input. rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal opera- tion. exit from reset places the device in asynchronous read array mode. wp# input w rite pr otect: active low input. wp# low enables the lock-down mechanism. blocks in lock-down cannot be unlocked with the unlock command. wp# high overrides the lock- down function enabling blocks to be erased or programmed using software commands. note: designs not using wp# for protection could tie it to v ccq or v ss without additional capacitor. we# input w rite enable: active low input. we# controls writes to the device. address and data are latched on the rising edge of we# or ce#, whichever occurs first. v pp power/input erase and pr ogram power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v ppl for in-system program and erase operations. t o accommodate resistor or diode drops from the system supply , the v ih level of v pp can be as low as v ppl,min . v pp must remain above v ppl,min to perform in-system modification. v pp may be 0v during read op- erations. v pp can be connected to 9v for a cumulative total not to exceed 80 hours. extended use of this pin at 9v may reduce block cycling capability. dq[15:0] input/output data input/output: inputs data and commands during write cycles; outputs data during memory , status register , protection register , and read configuration register reads. data balls float when the ce# or oe# are de-asserted. data is internally latched during writes. 512mb, 1gb, 2gb: p30-65nm signal descriptions pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 15 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 4: tsop and easy bga signal descriptions (continued) symbol type name and function wait output w ait: indicates data valid in synchronous array or non-array burst reads. read configura- tion register bit 10 (rcr.10, wt) determines its polarity when asserted. this signal's active output is v ol or v oh when ce# and oe# are v il . w ait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, this signal indicates invalid data when as- serted and valid data when de-asserted. ? in asynchronous page mode, and all write modes, this signal is de-asserted. v cc power device core power supply: core (logic) source voltage. writes to the array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. v ccq power output power supply: output-driver source voltage. v ss power ground: connect to system ground. do not float any v ss connection. rfu reserved for futur e use: reserved by micron for future device functionality and en- hancement. these should be treated in the same way as a du signal. du do not use: do not connect to any other signal, or power supply; must be left floating. nc no connect: no internal connection; can be driven or floated. 512mb, 1gb, 2gb: p30-65nm signal descriptions pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 16 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bus operations ce# l o w and rst# high enable read oper ations . the device inter nally decodes up- per addr ess inputs to deter mine the accessed block. ad v# l o w opens the inter nal ad- dr ess latches . oe# l o w activ ates the outputs and gates selected data onto the i/o bus . b us cy cles to/fr om the device confor m to standar d micr opr ocessor bus oper ations . b us operations and the logic levels that must be applied to the device control signal inputs are shown here. table 5: bus operations bus operation rst# clk adv# ce# oe# we# wait dq[15:0] notes read asynchronous h x l l l h de-asserted output - synchronous h run- ning l l l h driven output - write h x l l h l high-z input 1 output disable h x x l h h high-z high-z 2 standby h x x h x x high-z high-z 2 reset l x x x x x high-z high-z 2, 3 notes: 1. refer to the device command bus cycles for valid dq[15:0] during a write operation. 2. x = "dont care" (h or l). 3. rst# must be at v ss 0.2v to meet the maximum specified power -down current. read t o per for m a read oper ation, rst# and we# must be de-asser ted while ce# and oe# ar e asser ted. ce# is the device-select contr ol. when asser ted, it enables the device . oe# is the data-output contr ol. when asser ted, the addr essed flash memor y data is dr iv en onto the i/o bus . w rite t o per for m a write oper ation, both ce# and we# ar e asser ted while rst# and oe# ar e de-asser ted. d ur ing a write oper ation, addr ess and data ar e latched on the r ising edge of we# or ce#, whichev er occurs first. the c ommand b us c y cles table sho ws the bus cy cle sequence for each of the suppor ted device commands , while the c ommand c odes and d efinitions table descr ibes each command. n ote: write oper ations with inv alid v c c and/or v pp v oltages can pr oduce spur ious r e- sults and should not be attempted. output disable when oe# is de-asser ted, device outputs dq[15:0] ar e disabled and placed in h igh-z state , w ait is also placed in h igh-z. standby when ce# is de-asserted the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, inde- pendent of the level placed on oe#. standby current (i ccs ) is the average current meas- 512mb, 1gb, 2gb: p30-65nm bus operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 17 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ur ed o v er any 5ms time inter v al, 5 s after ce# is de-asser ted. d ur ing standb y , av er age curr ent is measur ed o v er the same time inter v al 5 s after ce# is de-asser ted. when the device is deselected (while ce# is de-asser ted) dur ing a pr ogram or erase oper ation, it continues to consume activ e po w er until the pr ogram or erase oper a- tion is completed. reset as with any automated device , it is impor tant to asser t rst# when the system is r eset. when the system comes out of r eset, the system pr ocessor attempts to r ead fr om the device if it is the system boot device . i f a cpu r eset occurs with no device r eset, impr op- er cpu initialization may occur because the device may be pr o viding status infor ma- tion r ather than arr ay data. m icr on devices enable pr oper cpu initialization follo wing a system r eset thr ough the use of the rst# input. rst# should be contr olled b y the same lo w-tr ue r eset signal that r esets the system cpu. after initial po w er -up or r eset, the device defaults to asynchr onous r ead arr ay mode , and the status r egister is set to 0x80. asser ting rst# de-ener giz es all inter nal cir cuits , and places the output dr iv ers in h igh-z. when rst# is asser ted, the device shuts do wn the oper ation in pr ogr ess , a pr ocess which takes a minimum amount of time to com- plete . when rst# has been de-asser ted, the device is r eset to asynchr onous r ead arr ay state . when device r etur ns fr om a r eset (rst# de-asser ted), a minimum wait is r equir ed be- for e the initial r ead access outputs v alid data. also , a minimum delay is r equir ed after a r eset befor e a wr ite cy cle can be initiated. after this wake-up inter v al passes , nor mal op- er ation is r estor ed. n ote: i f rst# is asser ted dur ing a pr ogram or erase oper ation, the oper ation is ter - minated and the memor y contents at the abor ted location (for a pr ogr am) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. 512mb, 1gb, 2gb: p30-65nm bus operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 18 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device command codes the system cpu pr o vides contr ol of all in-system read , write, and erase oper ations of the device via the system bus . the device manages all block-er ase and wor d-pr ogr am algor ithms . d evice commands ar e wr itten to the cui to contr ol all device oper ations . the cui does not occup y an addr essable memor y location; it is the mechanism thr ough which the device is contr olled. note: for a dual device, all setup commands should be re-issued to the device when a different die is selected. table 6: command codes and definitions mode device mode code description read read array 0xff places the device in read array mode. array data is output on dq[15:0]. read status register 0x70 places the device in read status register mode. the device enters this mode after a program or erase command is issued. status register data is output on dq[7:0]. read device id or read configuration register 0x90 places device in read device identifier mode. subsequent reads output manufacturer/device codes, configuration register data, block lock sta- tus, or protection register data on dq[15:0]. read cfi 0x98 places the device in read cfi mode. subsequent reads output cfi infor- mation on dq[7:0]. clear status register 0x50 the device sets status register error bits. the clear status register com- mand is used to clear the sr error bits. write word program setup 0x40 first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the device executes the programming algorithm at the ad- dressed location. during program operations, the device responds only to read st a tus register and program suspend commands. ce# or oe# must be toggled to update the status register in asynchro- nous read. ce# or adv# must be toggled to update the status register data for synchronous non-array reads. the read array command must be issued to read array data after programming has finished. buffered program 0xe8 this command loads a variable number of words up to the buffer size of 512 words onto the program buffer. buffered program confirm 0xd0 the confirm command is issued after the data streaming for writing into the buffer is completed. the device then performs the buffered program algorithm, writing the data from the buffer to the memory array. befp setup 0x80 first cycle of a two-cycle command; initiates buf fered enhanced factory program mode (befp). the cui then waits for the befp confirm com- mand, 0xd0, that initiates the befp algorithm. all other commands are ignored when befp mode begins. befp confirm 0xd0 if the previous command was befp setup (0x80), the cui latches the address and data, and prepares the device for befp mode. 512mb, 1gb, 2gb: p30-65nm device command codes pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 19 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 6: command codes and definitions (continued) mode device mode code description erase block erase setup 0x20 first cycle of a two-cycle command; prepares the cui for a block erase operation. the device performs the erase algorithm on the block addressed by the erase confirm command. if the next com- mand is not the erase confirm (0xd0) command, the cui sets status register bits sr4 and sr5, and places the device in read status register mode. block erase confirm 0xd0 if the first command was block erase setup (0x20), the cui latches the address and data, and the device erases the addressed block. dur - ing block erase operations, the device responds only to read st a tus register and erase suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the status register data for synchronous non-ar- ray reads. suspend program or erase suspend 0xb0 this command issued to any device address initiates a suspend of the currently-executing program or block erase operation. the status register indicates successful suspend operation by setting either sr2 (program suspended) or sr6 (erase suspended), along with sr7 (ready). the device remains in the suspend mode regardless of control signal states (except for rst# asserted). suspend resume 0xd0 this command issued to any device address resumes the suspended program or block erase operation. protection block lock setup 0x60 first cycle of a two-cycle command; prepares the cui for block lock con- figuration changes. if the next command is not block lock (0x01), block unlock (0xd0), or block lock down (0x2f), the cui sets sta- tus register bits sr5 and sr4, indicating a command sequence error. block lock 0x01 if the previous command was block lock setup (0x60), the addressed block is locked. block unlock 0xd0 if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock down state, the op- eration has no effect. block lock down 0x2f if the previous command was block lock setup (0x60), the addressed block is locked down. otp register or lock register program set- up 0xc0 first cycle of a two-cycle command; prepares the device for a otp reg- ister or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm to program data the otp array. configuration read configuration register setup 0x60 first cycle of a two-cycle command; prepares the cui for device read configuration. if the set read configura tion register command (0x03) is not the next command, the cui sets status register bits sr4 and sr5, indicating a command sequence error. read configuration register 0x03 if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[16:1] to the read con- figuration register for easy bga and tsop, a[15:0] for quad+. follow- ing a configure read configuration register command, subse- quent read operations access array data. 512mb, 1gb, 2gb: p30-65nm device command codes pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 20 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 6: command codes and definitions (continued) mode device mode code description blank check block blank check 0xbc first cycle of a two-cycle command; initiates the blank check opera- tion on a main block. block blank check confirm 0xd0 second cycle of blank check command sequence; it latches the block address and executes blank check on the main array block. efi extended function interface 0xeb first cycle of a multiple-cycle command; initiate operation using exten- ded function interface. the second cycle is a sub-op-code, the data written on third cycle is one less than the word count; the allowable value on this cycle are 0C511. the subsequent cycles load data words in- to the program buffer at a specified address until word count is ach- ieved. 512mb, 1gb, 2gb: p30-65nm device command codes pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 21 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device command bus cycles d evice oper ations ar e initiated b y wr iting specific device commands to the command user interface (cui). several commands are used to modify array data including word program and block erase commands. writing either command to the cui initiates a sequence of internally timed functions that culminate in the completion of the re- quested task. however, the operation can be aborted by either asserting rst# or by is- suing an appropriate suspend command. table 7: command bus cycles mode command bus cycles first bus cycle second bus cycle op addr 1 data 2 op addr 1 data 2 read read array 1 write dna 0xff C C C read device identifier 2 write dna 0x90 read dba + ia id read cfi 2 write dna 0x98 read dba + cfi-a cfi-d read status register 2 write dna 0x70 read dna srd clear status register 1 write dna 0x50 C C C program word program 2 write wa 0x40 write wa wd buffered program 3 >2 write wa 0xe8 write wa n - 1 buffered enhanced f actor y program (befp) 4 >2 write wa 0x80 write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1 write dna 0xb0 C C C program/erase resume 1 write dna 0xd0 C C C protection block lock 2 write ba 0x60 write ba 0x01 block unlock 2 write ba 0x60 write ba 0xd0 block lock down 2 write ba 0x60 write ba 0x2f program otp register 2 write pra 0xc0 write otp-ra otp-d program lock register 2 write lra 0xc0 write lra lrd configuration configure read configuration register 2 write rcd 0x60 write rcd 0x03 blank check block blank check 2 write ba 0xbc write ba d0 efi extended function interface 5 >2 write wa 0xeb write wa sub-op code notes: 1. first command cycle address should be the same as the operations target address. dba = device base address (needed for dual die 512mb device); dna = address within the de- vice; ia = identification code address of fset; cfi-a = read cfi address of fset; w a = w ord address of memory location to be written; ba = address within the block; otp-ra = pro- tection register address; lra = lock register address; rcd = read configuration register data on a[16:1] for easy bga and tsop , a[15:0] for quad+ package. 2. id = identifier data; cfi-d = cfi data on dq[15:0]; srd = status register data; wd = w ord data; n = w ord count of data to be loaded into the write buf fer; otp-d = protection register data; lrd = lock register data. 512mb, 1gb, 2gb: p30-65nm device command bus cycles pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 22 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buf fer . this is followed by up to 512 words of data. then the confirm command (0xd0) is issued, triggering the array programming operation. 4. the confirm command (0xd0) is followed by the buf fer data. 5. the second cycle is a sub-op-code, the data written on third cycle is n-1; 1 n 512. the subsequent cycles load data words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the final cycle is the con- firm cycle 0xd0). 512mb, 1gb, 2gb: p30-65nm device command bus cycles pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 23 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read operations the device suppor ts two r ead modes: asynchr onous page mode and synchr onous burst mode . asynchr onous page mode is the default r ead mode after device po w er -up or a r e- set. u nder asynchr onous page mode , the device can also per for m single wor d r ead. the r ead configur ation r egister must be configur ed to enable synchr onous burst r eads of the arr ay . the device can be in any of four r ead states: r ead arr ay , r ead identifier , r ead status , or r ead cfi. u pon po w er -up , or after a r eset, the device defaults to r ead arr ay . t o change the r ead state , the appr opr iate read command must be wr itten to the device . asynchr onous single w or d read t o per for m an asynchr onous single wor d r ead, an addr ess is dr iv en onto the addr ess bus , and ce# is asser ted. n ote: t o per for m an asynchr onous single wor d r ead for a t sop package , ad v# must be l o w thr oughout the read cy cle . f or an easy bga package , ad v# can be dr iv en high to latch the addr ess or be held l o w thr oughout the read cy cle . we# and rst# must alr eady hav e been de-asser ted. w ait is set to a de-asser ted state dur ing single wor d mode , as deter mined b y bit 10 of the r ead configur ation r egister . clk is not used for asynchr onous single wor d r eads , and is ignor ed. i f asynchr onous r eads ar e to be per for med only , clk should be tied to a v alid v ih or v ss lev el, w ait can be floated, and ad v# must be tied to gr ound. after oe# is asser ted, the data is dr iv en onto dq[15:0] after an initial access time t a v q v or t gl q v delay . asynchr onous page mode read (easy bga only) n ote: asynchr onous p age m ode r ead is suppor ted only in the main arr ay . f ollo wing a device po w er -up or r eset, asynchr onous page mode is the default r ead mode and the device is set to r ead arr ay . h o w ev er , to per for m arr ay r eads after any other device oper ation ( write oper ation), the read arra y command must be issued in or - der to r ead fr om the arr ay . asynchr onous page mode r eads can only be per for med when r ead configur ation r egis- ter bit r cr15 is set. t o per for m an asynchr onous page-mode r ead, an addr ess is dr iv en onto the addr ess bus , and ce# and ad v# ar e asser ted. we# and rst# must alr eady hav e been de-asser - ted. w ait is de-asser ted dur ing asynchr onous page mode . ad v# can be dr iv en high to latch the addr ess , or it must be held l o w thr oughout the read cy cle . clk is not used for asynchr onous page mode r eads , and is ignor ed. i f only asynchr onous r eads ar e to be per for med, clk should be tied to a v alid v ih or v ss lev el, w ait signal can be floated, and ad v# must be tied to gr ound. arr ay data is dr iv en onto dq[15:0] after an initial ac- cess time t a v q v delay . i n asynchr onous page mode , 16 data wor ds ar e sensed simultaneously fr om the arr ay and loaded into an inter nal page buffer . the buffer wor d corr esponding to the initial addr ess on the addr ess bus is dr iv en onto dq[15:0] after the initial access delay . the lowest four address bits determine which word of the 16-word page is output from the data buffer at any given time. 512mb, 1gb, 2gb: p30-65nm read operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 24 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
synchr onous burst mode read (easy bga only) r ead configur ation r egister bits r cr[15:0] must be set befor e synchr onous burst oper a- tion can be per for med. s ynchr onous burst mode can be per for med for both arr ay and non-arr ay r eads such as r ead id , r ead status , or r ead quer y . t o per for m a synchr onous burst r ead, an initial addr ess is dr iv en onto the addr ess bus , and ce# and ad v# ar e asser ted. we# and rst# must alr eady hav e been de-asser ted. ad v# is asser ted, and then de-asser ted to latch the addr ess . alter nately , ad v# can r e- main asser ted thr oughout the burst access , in which case the addr ess is latched on the next v alid clk edge while ad v# is asser ted. d ur ing synchr onous arr ay and non-arr ay r ead modes , the first wor d is output fr om the data buffer on the next v alid clk edge after the initial access latency delay . s ubsequent data is output on v alid clk edges follo wing a minimum delay . h o w ev er , for a synchr o- nous non-arr ay r ead, the same wor d of data will be output on successiv e clock edges until the burst length r equir ements ar e satisfied. r efer to the timing diagr ams for mor e detailed infor mation. read cfi the read cfi command instr ucts the device to output cfi data when r ead. s ee c om- mon f lash i nter face for details on issuing the read cfi command, and for details on addr esses and offsets within the cfi database . read device id the read device identifier command instructs the device to output manufacturer code, device identifier code, block lock status, protection register data, or configuration register data. table 8: device id information item address data manufacturer code 0x00 0x89 device id code 0x01 id (see the device id codes table ) block lock configuration block is unlocked block is locked block is not locked down block is locked down block base address + 0x02 lock bit dq 0 = 0b0 dq 0 = 0b1 dq 1 = 0b0 dq 1 = 0b1 read configuration register 0x05 rcr contents general purpose register device base address + 0x07 general purpose register data lock register 0 0x80 pr-lk0 data 64-bit factory-programmed otp register 0x81C0x84 factory otp register data 64-bit user-programmable otp register 0x85C0x88 user otp register data lock register 1 0x89 pr-lk1 otp register lock data 128-bit user-programmable protection regis- ters 0x8aC0x109 otp register data 512mb, 1gb, 2gb: p30-65nm synchronous burst mode read (easy bga only) pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 25 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device id codes table 9: device id codes id code type device density device identifier codes Ct (top parameter) Cb (bottom parameter) Ce/f (symmetrical blocks) device code 512mb 8960 8961 8999 1gb 8962 8963 899a note: 1. the 2gb devices do not have a unique device id associated with them. each die within the stack can be identified by device id codes. 512mb, 1gb, 2gb: p30-65nm device id codes pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 26 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
pr ogram operations s uccessful pr ogr amming r equir es the addr essed block to be unlocked. i f the block is locked do wn, wp# must be de-asser ted and the block must be unlocked befor e at- tempting to pr ogr am the block. a ttempting to pr ogr am a locked block causes a pr ogr am err or (sr4 and sr1 set) and ter mination of the oper ation. s ee s ecur ity m odes for details on locking and unlocking blocks . w or d pr ogramming (40h) w or d pr ogr amming oper ations ar e initiated b y wr iting the w ord pr ogram setup command to the device (see the c ommand c odes and d efinitions table). this is fol- lo w ed b y a second wr ite to the device with the addr ess and data to be pr ogr ammed. the device outputs status r egister data when r ead (see the w or d p r ogr am f lo w char t). v pp must be abo v e v pplk , and within the specified v ppl min/ma x v alues . d ur ing pr ogr amming, the device executes a sequence of inter nally -timed ev ents that pr ogr am the desir ed data bits at the addr essed location, and v er ifies that the bits ar e sufficiently pr ogr ammed. p r ogr amming the arr ay changes 1s to 0s . m emor y arr ay bits that ar e 0s can be changed to 1s only b y er asing the block (see e r ase o per ations). the status r egister can be examined for pr ogr amming pr ogr ess and err ors b y r eading at any addr ess . the device r emains in the r ead status r egister state until another com- mand is wr itten to the device . sr7 indicates the pr ogr amming status while the sequence executes . c ommands that can be issued to the device dur ing pr ogr amming ar e pr ogram susp end , read st a- tus register, read de vice identifier, read cfi, and read arra y (this r etur ns unkno wn data). when pr ogr amming has finished, sr4 (when set) indicates a pr ogr amming failur e . i f sr3 is set, the device could not per for m the w ord pr ogramming oper ation because v pp was outside of its acceptable limits . i f sr1 is set, the w ord pr ogramming oper a- tion attempted to pr ogr am a locked block, causing the oper ation to abor t. b efor e issuing a new command, the status r egister contents should be examined and then clear ed using the clear st a tus register command. any v alid command can follo w , when wor d pr ogr amming has completed. buf fer ed pr ogramming (e8h, d0h) the device featur es a 512-wor d buffer to enable optimum pr ogr amming per for mance . f or buffer ed pr ogr amming, data is first wr itten to an on-chip wr ite buffer . then the buf- fer data is pr ogr ammed into the arr ay in buffer -siz e incr ements . this can impr o v e sys- tem pr ogr amming per for mance significantly o v er non-buffer ed pr ogr amming. when the b uffered pr ogramming setup command is issued, status r egister in- for mation is updated and r eflects the av ailability of the buffer . sr7 indicates buffer av ailability : if set, the buffer is av ailable; if clear ed, the buffer is not av ailable . n ote: the device default state is to output sr data after the b uffered pr ogram- ming setup command. ce# and oe# l o w dr iv e device to update status r egister . i t is not allowed to issue 70h to read sr data after e8h command; otherwise, 70h would be counted as word count. 512mb, 1gb, 2gb: p30-65nm program operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 27 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
o n the next wr ite , a wor d count is wr itten to the device at the buffer addr ess . this tells the device ho w many data wor ds will be wr itten to the buffer , up to the maximum siz e of the buffer . o n the next wr ite , a device star t addr ess is giv en along with the first data to be wr itten to the flash memor y arr ay . s ubsequent wr ites pr o vide additional device addr esses and da- ta. all data addr esses must lie within the star t addr ess plus the wor d count. o ptimum pr ogr amming per for mance and lo w er po w er usage ar e obtained b y aligning the star ting addr ess at the beginning of a 512-wor d boundar y (a[9:1] = 0x00 for easy bga and t sop , a[8:0] for q u ad+ package; see p ar t n umber ing i nfor mation). the maximum buffer siz e would be 256-wor d if the misaligned addr ess r ange is cr ossing a 512-wor d boundar y dur ing pr ogr amming. after the last data is wr itten to the buffer , the b uffered pr ogramming c onfirm command must be issued to the or iginal block addr ess . the device begins to pr ogr am buffer contents to the arr ay . i f a command other than the b uffered pr ogramming c onfirm command is wr itten to the device , a command sequence err or occurs and sr[7,5,4] ar e set. i f an err or occurs while wr iting to the arr ay , the device stops pr ogr am- ming, and sr[7,4] ar e set, indicating a pr ogr amming failur e . when buffer ed pr ogr amming has completed, additional buffer wr ites can be initiated b y issuing another b uffered pr ogramming setup command and r epeating the buffer ed pr ogr am sequence . b uffer ed pr ogr amming may be per for med with v pp = v ppl or v pp h (see o per ating c onditions for limitations when oper ating the device with v pp = v pp h ). i f an attempt is made to pr ogr am past an er ase-block boundar y using the b uffered pr ogram command, the device abor ts the oper ation. this gener ates a command se- quence err or , and sr[5,4] ar e set. i f buffer ed pr ogr amming is attempted while v pp is at or belo w v pplk , sr[4,3] ar e set. i f any err ors ar e detected that hav e set status r egister bits , the status r egister should be clear ed using the clear st a tus register command. buf fer ed enhanced factory pr ogramming (80h, d0h) b uffer ed enhanced factor y pr ogr amming (befp) speeds up multilev el cell (ml c) pr o- gr amming. the enhanced pr ogr amming algor ithm used in befp eliminates tr aditional pr ogr amming elements that dr iv e up o v er head in device pr ogr ammer systems . befp consists of thr ee phases: setup , pr ogr am/v er ify , and exit (see the befp f lo w char t). i t uses a wr ite buffer to spr ead ml c pr ogr am per for mance acr oss 512 data wor ds . v er ifi- cation occurs in the same phase as pr ogr amming to accur ately pr ogr am the cell to the corr ect bit state . a single two-cy cle command sequence pr ogr ams the entir e block of data. this en- hancement eliminates thr ee wr ite cy cles per buffer : two commands and the wor d count for each set of 512 data wor ds . h ost pr ogr ammer bus cy cles fill the device wr ite buffer follo w ed b y a status check. sr0 indicates when data fr om the buffer has been pr ogr am- med into sequential arr ay locations . f ollo wing the buffer -to-flash arr ay pr ogr amming sequence , the device incr ements in- ternal addressing to automatically select the next 512-word array boundary. this aspect of befp saves host programming equipment the address bus setup overhead. 512mb, 1gb, 2gb: p30-65nm program operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 28 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
with adequate continuity testing, programming equipment can rely on the devices in- ternal verification to ensure that the device has programmed properly. this eliminates the external post-program verification and its associated overhead. table 10: befp requirements parameter/issue requirement notes case temperature t c = 30c 10c v cc nominal v cc v pp driven to v pph setup and confirm target block must be unlocked before issuing the befp setup and confirm commands. programming the first-word address (w a0) of the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. buffer alignment wa0 must align with the start of an array buffer boundary. 1 note: 1. word buffer boundaries in the array are determined by the lowest 9 address bits (0x000 through 0x1ff). the alignment start point is 0x000. table 11: befp considerations parameter/issue requirement notes cycling for optimum performance, cycling must be limited below 50 erase cycles per block. 1 programming blocks befp programs one block at a time; all buffer data must fall within a single block. 2 suspend befp cannot be suspended. programming the ar- ray programming to the array can occur only when the buffer is full. 3 notes: 1. some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly . 2. if the internal address counter increments beyond the block's maximum address, ad- dressing wraps around to the beginning of the block. 3. if the number of words is less than 512, remaining locations must be filled with 0xffff . befp s etup p hase: after r eceiving the befp setup and c onfirm command se- quence , sr7 (r eady) is clear ed, indicating that the device is busy with befp algor ithm star tup . a delay befor e checking sr7 is r equir ed to allo w the device enough time to per - for m all of its setups and checks (block lock status , v pp lev el, etc .). i f an err or is detected, sr4 is set and befp oper ation ter minates . i f the block was found to be locked, sr1 is also set. sr3 is set if the err or occurr ed due to an incorr ect v pp lev el. n ote: r eading fr om the device after the befp setup and c onfirm command se- quence outputs status r egister data. do not issue the read st a tus register com- mand; it will be interpr eted as data to be loaded into the buffer . befp p r ogr am/v er ify p hase: after the befp setup phase has completed, the host pr o- gr amming system must check sr[7,0] to deter mine the av ailability of the wr ite buffer for data str eaming. sr7 clear ed indicates the device is busy and the befp pr ogr am/v er i- fy phase is activ ated. sr0 indicates the wr ite buffer is av ailable . t wo basic sequences r epeat in this phase: loading of the wr ite buffer , follo w ed b y buffer data programming to the array. for befp, the count value for buffer loading is always 512mb, 1gb, 2gb: p30-65nm program operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 29 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
the maximum buffer siz e of 512 wor ds . d ur ing the buffer -loading sequence , data is stor - ed to sequential buffer locations star ting at addr ess 0x00. p r ogr amming of the buffer contents to the arr ay star ts as soon as the buffer is full. i f the number of wor ds is less than 512, the r emaining buffer locations must be filled with 0xffff . n ote: the buffer must be completely filled for pr ogr amming to occur . s upplying an ad- dr ess outside of the curr ent block's r ange dur ing a buffer -fill sequence causes the algo- r ithm to exit immediately . any data pr eviously loaded into the buffer dur ing the fill cy - cle is not pr ogr ammed into the arr ay . the star ting addr ess for data entr y must be buffer siz e aligned; if not, the befp algo- r ithm will be abor ted, the pr ogr am fails , and the (sr4) flag will be set. d ata wor ds fr om the wr ite buffer ar e dir ected to sequential memor y locations in the ar - r ay ; pr ogr amming continues fr om wher e the pr evious buffer sequence ended. the host pr ogr amming system must poll sr0 to deter mine when the buffer pr ogr am sequence completes . sr0 clear ed indicates that all buffer data has been tr ansferr ed to the arr ay ; sr0 set indicates that the buffer is not av ailable y et for the next fill cy cle . the host sys- tem may check full status for err ors at any time , but it is only necessar y on a block basis after befp exit. after the buffer fill cy cle , no write cy cles should be issued to the de- vice until sr0 = 0 and the device is r eady for the next buffer fill. n ote: any spur ious wr ites ar e ignor ed after a b uffer fill oper ation and when inter nal pr ogr am is pr oceeding. the host pr ogr amming system continues the befp algor ithm b y pr o viding the next gr oup of data wor ds to be wr itten to the buffer . alter nativ ely , it can ter minate this phase b y changing the block addr ess to one outside of the curr ent blocks r ange . the pr ogr am/v er ify phase concludes when the pr ogr ammer wr ites to a differ ent block addr ess; data supplied must be 0xffff . u pon pr ogr am/v er ify phase completion, the de- vice enters the befp exit phase . pr ogram suspend i ssuing the pr ogram susp end command while pr ogr amming suspends the pr o- gr amming oper ation. this allo ws data to be accessed fr om the device other than the one being pr ogr ammed. the pr ogram susp end command can be issued to any de- vice addr ess . a pr ogram oper ation can be suspended to per for m r eads only . a ddition- ally , a pr ogram oper ation that is r unning dur ing an er ase suspend can be suspended to per for m a read oper ation. when a pr ogr amming oper ation is executing, issuing the pr ogram susp end com- mand r equests the device to suspend the pr ogr amming algor ithm at pr edeter mined points . the device continues to output status r egister data after the pr ogram sus- p end command is issued. p r ogr amming is suspended when sr[7,2] ar e set. t o r ead data fr om the device , the read arra y command must be issued. read arra y , read st a tus register, read de vice identifier, read cfi, and pr ogram re- sume v alid commands dur ing a pr ogr am suspend. d ur ing a pr ogr am suspend, de-asser ting ce# places the device in standb y , r educing ac- tiv e curr ent. v pp must r emain at its pr ogr amming lev el, and wp# must r emain un- changed while in program suspend. if rst# is asserted, the device is reset. 512mb, 1gb, 2gb: p30-65nm program operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 30 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
pr ogram resume the resume command instr ucts the device to continue pr ogr amming, and automati- cally clears sr[7,2]. this command can be wr itten to any addr ess . i f err or bits ar e set, the status r egister should be clear ed befor e issuing the next command. rst# must r e- main de-asser ted. pr ogram pr otection when v pp = v il , absolute har dwar e wr ite pr otection is pr o vided for all device blocks . i f v pp is at or belo w v pplk , pr ogr amming oper ations halt and sr3 is set, indicating a v pp - lev el err or . b lock lock r egisters ar e not affected b y the v oltage lev el on v pp ; they may still be pr ogr ammed and r ead, ev en if v pp is less than v pplk . figur e 8: example v pp supply connections v cc v pp v cc v pp 10k < -factory programming with v pp = v pph -complete with program/erase protection when v < pp v pplk v cc v cc v pp -low voltage programming only -full device protection unavailable -low voltage programming only -logic control of device protection v cc prot# v cc v pp -low voltage and factory programming v cc v pp v cc v pp v pph = 512mb, 1gb, 2gb: p30-65nm program operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 31 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
erase operations block erase command erase oper ations ar e per for med on a block basis . an entir e block is er ased each time a bl ock erase command sequence is issued, and only one block is er ased at a time . when a block is er ased, each bit within that block r eads as a logical 1. a bl ock erase oper ation is initiated b y wr iting the bl ock erase setup command to the addr ess of the block to be er ased, follo w ed b y the bl ock erase c onfirm com- mand. i f the device is placed in standb y (ce# de-asser ted) dur ing a bl ock erase oper - ation, the device completes the oper ation befor e enter ing standb y . the v pp v alue must be abo v e v pplk and the block must be unlocked. d ur ing a bl ock erase oper ation, the device executes a sequence of inter nally -timed ev ents that conditions , er ases , and v er ifies all bits within the block. e r asing the arr ay changes the v alue in each cell fr om a 1 to a 0. m emor y block arr ay cells that with a v alue of 1 can be changed to 0 only b y pr ogr amming the block. the status r egister can be examined for block er ase pr ogr ess and err ors b y r eading any addr ess . the device r emains in the r ead status r egister state until another command is wr itten. sr0 indicates whether the addr essed block is er asing. sr7 is set upon er ase completion. sr7 indicates block er ase status while the sequence executes . when the bl ock erase oper ation has completed, sr5 = 1 (set) indicates an er ase failur e . sr3 = 1 indicates that the device could not per for m the bl ock erase oper ation because v pp was outside of its acceptable limits . sr1 = 1 indicates that the bl ock erase oper ation attempted to er ase a locked block, causing the oper ation to abor t. b efor e issuing a new command, the status r egister contents should be examined and then clear ed using the clear st a tus register command. any v alid command can follo w after the bl ock erase oper ation has completed. the bl ock erase oper ation is abor ted b y per for ming a r eset or po w er ing do wn the device . i n either case , data integr ity cannot be ensur ed, and it is r ecommended to er ase again the blocks abor ted. blank check command the bl ank check oper ation deter mines whether a specified main block is blank; that is , completely er ased. o ther than a bl ank check oper ation, only a bl ock erase op- er ation can ensur e a block is completely er ased. bl ank check is especially useful when a bl ock erase oper ation is interr upted b y a po w er loss ev ent. a bl ank check oper ation can apply to only one block at a time . the only oper ation allo w ed simultaneously is a read st a tus register oper ation. susp end and re- sume oper ations and a bl ank check oper ation ar e mutually ex clusiv e . a bl ank check oper ation is initiated b y wr iting the bl ank check setup command to the block addr ess , follo w ed b y the check c onfirm command. when a successful command sequence is enter ed, the device automatically enters the r ead status state . the device then reads the entire specified block and determines whether any bit in the block is programmed or over-erased. 512mb, 1gb, 2gb: p30-65nm erase operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 32 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bl ank check oper ation pr ogr ess and err ors ar e deter mined b y r eading the status r eg- ister at any addr ess within the block being accessed. sr7 = 0 is a bl ank check busy status . sr7 = 1 is a bl ank check oper ation complete status . the status r egister should be checked for any err ors and then clear ed. i f the bl ank check oper ation fails , mean- ing the block is not completely er ased, sr5 = 1. ce# or oe# toggle (dur ing polling) up- dates the status r egister . the read st a tus register command must always be follo w ed b y a clear st a tus register command. the device r emains in status r egister mode until another com- mand is wr itten to the device . any command can follo w once the bl ank check com- mand is complete . erase suspend command the erase susp end command suspends a bl ock erase oper ation that is in pr o- gr ess , enabling access to data in memor y locations other than the one being er ased. the erase susp end command can be issued to any device addr ess . a bl ock erase oper - ation can be suspended to per for m a w ord or b uffer pr ogram oper ation, or a read oper ation within any block ex cept the block that is er ase suspended. when a bl ock erase oper ation is executing, issuing the erase susp end command r equests the device to suspend the er ase algor ithm at pr edeter mined points . the device continues to output status r egister data after the erase susp end command is issued. b lock er ase is suspended when sr[7,6] ar e set. t o r ead data fr om the device (other than an er ase-suspended block), the read arra y command must be issued. d ur ing er ase suspend, a pr ogram command can be issued to any block other than the er ase-suspended block. b lock er ase cannot r esume until pr ogr am oper ations initiated dur ing er ase suspend complete . read arra y , read st a- tus register, read de vice identifier, read cfi, and erase resume ar e v alid commands dur ing er ase suspend. a dditionally , clear st a tus register, pr ogram, pr ogram susp end , bl ock l ock, bl ock unl ock, and bl ock l ock do wn ar e v alid commands dur ing an erase susp end oper ation. d ur ing an er ase suspend, de-asser ting ce# places the device in standb y , r educing activ e curr ent. v pp must r emain at a v alid lev el, and wp# must r emain unchanged while in er ase suspend. i f rst# is asser ted, the device is r eset. erase resume command the erase resume command instr ucts the device to continue er asing, and automati- cally clears sr[7,6]. this command can be wr itten to any addr ess . i f status r egister err or bits ar e set, the status r egister should be clear ed befor e issuing the next instr uction. rst# must r emain de-asser ted. erase pr otection when v pp = v il , absolute hardware erase protection is provided for all device blocks. if v pp is at or below v pplk , erase operations halt and sr3 is set indicating a v pp -level er- ror. 512mb, 1gb, 2gb: p30-65nm erase operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 33 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
security operations block locking i ndividual instant block locking is used to pr otect user code and/or data within the flash memor y arr ay . all blocks po w er -up in a locked state to pr otect arr ay data fr om be- ing alter ed dur ing po w er tr ansitions . any block can be locked or unlocked with no la- tency . locked blocks cannot be pr ogr ammed or er ased; they can only be r ead. s oftwar e-contr olled secur ity is implemented using the bl ock l ock and bl ock un- l ock commands . h ar dwar e-contr olled secur ity can be implemented using the bl ock l ock do wn command along with asser ting wp#. also , v pp data secur ity can be used to inhibit pr ogram and erase oper ations . block lock command t o lock a block, issue the bl ock l ock setup command, follo w ed b y the bl ock l ock command issued to the desir ed blocks addr ess . i f the set read c onfigura tion register command is issued after the bl ock l ock setup command, the device configur es the r cr instead. bl ock l ock and unl ock oper ations ar e not affected b y the v oltage lev el on v pp . the block lock bits may be modified and/or r ead ev en if v pp is at or belo w v pplk . block unlock command the bl ock unl ock command is used to unlock blocks . u nlocked blocks can be r ead, pr ogr ammed, and er ased. u nlocked blocks r etur n to a locked state when the device is r eset or po w er ed do wn. i f a block is in a lock-do wn state , wp# must be de-asser ted be- for e it can be unlocked. block lock down command a locked or unlocked block can be locked-do wn b y wr iting the bl ock l ock do wn command sequence . b locks in a lock-do wn state cannot be pr ogr ammed or er ased; they can only be r ead. h o w ev er , unlike locked blocks , their locked state cannot be changed b y softwar e commands alone . a locked-do wn block can only be unlocked b y issuing the bl ock unl ock command with wp# de-asser ted. t o r etur n an unlocked block to locked-do wn state , a bl ock l ock do wn command must be issued pr ior to changing wp# to v il . locked-do wn blocks r ev er t to the locked state upon r eset or po w er up the device . block lock status the read de vice identifier command is used to deter mine a blocks lock status . dq[1:0] display the addr essed blocks lock status; dq0 is the addr essed blocks lock bit, while dq1 is the addressed blocks lock-down bit. 512mb, 1gb, 2gb: p30-65nm security operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 34 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 9: block locking state diagram [000] program/erase allowed wp# = v il = 0 wp# = v il = 0 program/erase prevented (virtual lock-down) program/erase prevented wp# = v ih = 1 [110] [100] [001] [011] [111] [101] [010] (locked down) 2fh 2fh 2fh 2fh 01h d0h 01h/2fh 01h d0h d0h d0h, 01h, or 2fh (power-up/ reset default) (lock down disabled, wp# = v ih ) (power-up/ reset default) wp# toggle wp# toggle program/erase allowed wp# = v ih = 1 note: 1. d0h = unlock command; 01h = lock command; 60h (not shown) lock setup com- mand; 2fh = lock down command. block locking during suspend b lock lock and unlock changes can be per for med dur ing an er ase suspend. t o change block locking dur ing an erase oper ation, first issue the erase susp end command. m onitor the status r egister until sr7 and sr6 ar e set, indicating the device is suspended and r eady to accept another command. n ext, wr ite the desir ed lock command sequence to a block, which changes the lock state of that block. after completing bl ock l ock or bl ock unl ock oper ations , r e- sume the erase oper ation using the erase resume command. n ote: a bl ock l ock setup command follo w ed b y any command other than bl ock l ock, bl ock unl ock, or bl ock l ock do wn pr oduces a command sequence err or and set sr4 and sr5. i f a command sequence err or occurs dur ing an er ase suspend, sr4 and sr5 r emains set, ev en after the er ase oper ation is r esumed. u nless the s tatus r egister is clear ed using the clear st a tus register command befor e r esuming the erase op- er ation, possible er ase err ors may be masked b y the command sequence err or . if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is re- sumed. block lock operations cannot occur during a program suspend. 512mb, 1gb, 2gb: p30-65nm security operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 35 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
selectable otp blocks the o tp secur ity featur e on the device is backwar d-compatible to the earlier gener a- tion devices . c ontact y our local m icr on r epr esentativ e for details about its implementa- tion. passwor d access the passwor d access is a secur ity enhancement offer ed on the device . this featur e pr o- tects infor mation stor ed in arr ay blocks b y pr ev enting content alter ation or r eads until a v alid 64-bit passwor d is r eceiv ed. the passwor d access may be combined with nonv ola- tile pr otection and/or v olatile pr otection to cr eate a multi-tier ed solution. contact your micron sales office for further details concerning password access. 512mb, 1gb, 2gb: p30-65nm security operations pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 36 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
status register read status register t o r ead the status r egister , issue the read st a tus register command at any addr ess . s tatus r egister infor mation is av ailable at the addr ess that the read st a tus register, w ord pr ogram, or bl ock erase command is issued to . s tatus r egister data is auto- matically made av ailable follo wing a wor d pr ogr am, block er ase , or block lock com- mand sequence . r eads fr om the device after any of these command sequences will out- put the devices status until another v alid command is wr itten (e .g. read arra y com- mand). the status r egister is r ead using single asynchr onous mode or synchr onous burst mode r eads . s tatus r egister data is output on dq[7:0], while 0x00 is output on dq[15:8]. i n asynchr onous mode , the falling edge of oe# or ce# (whichev er occurs first) updates and latches the status r egister contents . h o w ev er , when r eading the status r egister in synchr onous burst mode , ce# or ad v# must be toggled to update status data. the device wr ite status bit (sr7) pr o vides the o v er all status of the device . sr[6:1] pr esent status and err or infor mation about the pr ogram, erase, susp end , v pp , and bl ock l ock oper ations . n ote: r eading the status r egister is a nonarr ay read oper ation. when the oper ation oc- curs in asynchr onous page mode , only the first data is v alid and all subsequent data ar e undefined. when the operation occurs in synchronous burst mode, the same data word requested will be output on successive clock edges until the burst length requirements are satisfied. t able 12: status register description notes apply to entire table bits name bit settings description 7 device write status (dws) 0 = busy 1 = ready status bit: indicates whether a program or erase command cycle is in progress. 6 erase suspend status (ess) 0 = not in ef fect 1 = in effect status bit: indicates whether an erase operation has been or is going to be suspended. 5:4 erase/blank check status (es) program status (ps) 00 = program/erase successful 01 = program error 10 = erase/blank check error 11 = command sequence error status/err or bit: indicates whether an erase/ blank check or program operation was success- ful. when an error is returned, the operation is aborted. 3 v pp status (vpps) 0 = within limits 1 = exceeded limits (v pp v pplk ) status bit: indicates whether a program/erase operation is within acceptable voltage range limits. 2 program suspend status (pss) 0 = not in ef fect 1 = in effect status bit: indicates whether a program opera- tion has been or is going to be suspended. 1 block lock status (bls) 0 = not locked 1 = locked (operation aborted) status bit: indicates whether a block is locked when a program or erase operation is initiated. 0 befp status (bws) 0 = befp complete 1 = befp in progress status bit: indicates whether befp data has com- pleted loading into the buffer. notes: 1. default value = 0x80. 2. always clear the status register prior to resuming erase operations. this eliminates sta- tus register ambiguity when issuing commands during erase suspend. if a command 512mb, 1gb, 2gb: p30-65nm status register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 37 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
sequence error occurs during an erase suspend, the status register contains the com- mand sequence error status (sr[7,5,4] set). when the erase operation resumes and fin- ishes, possible errors during the operation cannot be detected via the status register be- cause it contains the previous error status. 3. when bits 5:4 indicate a program/erase operation error , either a clear st a tus reg- ister 50h) or a reset command must be issued with a 15s delay . clear status register the clear st a tus register command clears the status r egister . i t functions inde- pendently of v pp . the device sets and clears sr[7,6,2], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command se- quence to avoid any ambiguity. a device reset also clears the status register. 512mb, 1gb, 2gb: p30-65nm status register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 38 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
configuration register read configuration register the r ead configur ation r egister (r cr) is a 16-bit r ead/wr ite r egister used to select bus r ead mode (synchr onous or asynchr onous) and to configur e device synchr onous burst r ead char acter istics . t o modify r cr settings , use the c onfigure read c onfigura- tion register command. r cr contents can be examined using the read de vice identifier command and then r eading fr om offset 0x05. o n po w er -up or exit fr om r e- set, the r cr defaults to asynchr onous mode . r cr bits ar e descr ibed in mor e detail be- lo w . n ote: r eading the configur ation r egister is a nonarr ay read oper ation. when the oper - ation occurs in asynchr onous page mode , only the first data is v alid, and all subsequent data ar e undefined. when the oper ation occurs in synchr onous burst mode , the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. table 13: read configuration register bits name settings/description 15 read mode (rm) 0 = synchronous burst mode read 1 = asynchronous page mode read (default) 14:11 latency count (lc[3:0]) 0000 = code 0 (reserved) 0001 = code 1 (reserved) 0010 = code 2 (reserved) 0011 = code 3 0100 = code 4 0101 = code 5 0110 = code 6 0111 = code 7 1000 = code 8 1001 = code 9 1010 = code 10 1011 = code11 1100 = code 12 1101 = code 13 1110 = code 14 1111 = code 15 (default) 10 wait polarity (wp) 0 = w ait signal is active low (default) 1 = wait signal is active high 9 reserved (r) default 0, nonchangeable 8 wait delay (wd) 0 = w ait de-asserted with valid data 1 = wait de-asserted one data cycle before valid data (default) 7 burst sequence (bs) default 0, nonchangeable 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) default 0, nonchangeable 3 burst wrap (bw) 0 = w rap; burst accesses wrap within burst length set by bl[2:0] 1 = no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 = 4-word burst 010 = 8-word burst 011 = 16-word burst 111 = continuous burst (default) (other bit settings are reserved) read mode the r ead mode (rm) bit selects synchr onous burst mode or asynchr onous page mode operation for the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. 512mb, 1gb, 2gb: p30-65nm configuration register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 39 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
latency count the latency count (l c) bits tell the device ho w many clock cy cles must elapse fr om the r ising edge of ad v# (or fr om the first v alid clock edge after ad v# is asser ted) until the first v alid data wor d is dr iv en to dq[15:0]. the input clock fr equency is used to deter - mine this v alue . the f irst a ccess latency c ount figur e sho ws the data output latency for differ ent l c settings . figur e 10: first access latency count code 1 ( reserved ) ( reserved ) code 6 code 5 code 4 code 3 code 2 code 0 ( reserved ) code 7 valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] dq[15:0] [d/q] clk [c] note: 1. first access latency count calculation: ? 1 / clk frequency = clk period (ns) ? n x (clk period) t a vqv (ns) C t chqv (ns) ? latency count = n 512mb, 1gb, 2gb: p30-65nm configuration register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 40 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 11: example latency count setting using code 3 clk ce# adv# a[max:1] d[15:0] t data 0 1 2 3 4 high-z code 3 address r103 data end of w or dline considerations e nd of wor dline (eo wl) wait states can r esult when the star ting addr ess of the burst op- er ation is not aligned to a 16-wor d boundar y ; that is , a[4:1] of the star t addr ess does not equal 0x0. the figur e belo w illustr ates the end of wor dline wait state(s) that occur after the first 16-wor d boundar y is r eached. the number of data wor ds and wait states is summar iz ed in the table belo w . figur e 12: end of w or dline timing diagram clk adv# eowl data oe# wait# a[max:1] dq[15:0] latency count data data address 512mb, 1gb, 2gb: p30-65nm configuration register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 41 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 14: end of wordline data and wait state comparison latency count 130nm 65nm data words wait states data words wait states 1 not supported not supported not supported not supported 2 4 0 to 1 not supported not supported 3 4 0 to 2 not supported not supported 4 4 0 to 3 not supported not supported 5 4 0 to 4 16 0 to 4 6 4 0 to 5 16 0 to 5 7 4 0 to 6 16 0 to 6 8 not supported not supported 16 0 to 7 9 16 0 to 8 10 16 0 to 9 11 16 0 to 10 12 16 0 to 11 13 16 0 to 12 14 16 0 to 13 15 16 0 to 14 w ait signal polarity and functionality the w ait polar ity ( wp) bit, r cr10 deter mines the asser ted lev el ( v oh or v ol ) of w ait . when wp is set, w ait is asser ted high (default). when wp is clear ed, w ait is asser ted l o w . the w ait signal changes state on v alid clock edges dur ing activ e bus cy cles (ce# asser ted, oe# asser ted, rst# de-asser ted). the w ait signal indicates data v alid when the device is oper ating in synchr onous mode (r cr15 = 0). the w ait signal is only de-asser ted when data is v alid on the bus . when the device is oper ating in synchr onous nonarr ay r ead mode , such as r ead status , r ead id , or r ead cfi, the w ait signal is also de-asser ted when data is v alid on the bus . w ait behavior dur ing synchr onous nonarr ay r eads at the end of wor dline wor ks corr ectly on- ly on the first data access. when the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, wait is set to a de-as- serted state as determined by rcr10. table 15: wait functionality table condition wait notes ce# = 1, oe# = x or ce# = 0, oe# = 1 high-z 1 ce# = 0, oe# = 0 active 1 synchronous array reads active 1 synchronous nonarray reads active 1 all asynchronous reads de-asserted 1 512mb, 1gb, 2gb: p30-65nm configuration register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 42 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 15: wait functionality table (continued) condition wait notes all writes high-z 1, 2 notes: 1. active means that w ait is asserted until data becomes valid, then deasserts. 2. when oe# = v ih during writes, w ait = high-z. w ait delay the w ait delay ( wd) bit contr ols the w ait asser tion delay behavior dur ing synchr o- nous burst r eads . w ait can be asser ted either dur ing or one data cy cle befor e v alid data is output on dq[15:0]. when wd is set, w ait is de-asser ted one data cy cle befor e v alid data (default). when wd is clear ed, w ait is de-asser ted during v alid data. burst sequence the burst sequence (bs) bit selects linear burst sequence (default). o nly linear burst se- quence is suppor ted. the synchr onous burst sequence for all burst lengths , as w ell as the effect of the burst wrap (bw) setting are shown below. table 16: burst sequence word ordering start addr ess (dec) burst w rap (rcr3) burst addressing sequence (dec) 4-w or d burst (bl[2:0] = 0b001) 8-w or d burst (bl[2:0] = 0b010) 16-w or d burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-414-15 0-1-2-3-4-5-6- 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-515-0 1-2-3-4-5-6-7- 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-615-0-1 2-3-4-5-6-7-8- 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-715-0-1-2 3-4-5-6-7-8-9- 4 0 4-5-6-7-0-1-2-3 4-5-6-7-815-0-1-2-3 4-5-6-7-8-9-10 5 0 5-6-7-0-1-2-3-4 5-6-7-8-915-0-1-2-3-4 5-6-7-8-9-10-11 6 0 6-7-0-1-2-3-4-5 6-7-8-9-1015-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 0 7-0-1-2-3-4-5-6 7-8-9-1015-0-1-2-3-4-5-6 7-8-9-10-11-12-13 ? ? ? ? ? ? 14 0 14-15-0-1-212-13 14-15-16-17-18-19-20- 15 0 15-0-1-2-313-14 15-16-17-18-19-20-21- ? ? ? ? ? ? 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-414-15 0-1-2-3-4-5-6- 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-515-16 1-2-3-4-5-6-7- 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-616-17 2-3-4-5-6-7-8- 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-717-18 3-4-5-6-7-8-9- 512mb, 1gb, 2gb: p30-65nm configuration register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 43 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 16: burst sequence word ordering (continued) start addr ess (dec) burst w rap (rcr3) burst addressing sequence (dec) 4-w or d burst (bl[2:0] = 0b001) 8-w or d burst (bl[2:0] = 0b010) 16-w or d burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 4 1 4-5-6-7-8-9-10-11 4-5-6-7-818-19 4-5-6-7-8-9-10 5 1 5-6-7-8-9-10-11-12 5-6-7-8-919-20 5-6-7-8-9-10-11 6 1 6-7-8-9-10-11-12-13 6-7-8-9-1020-21 6-7-8-9-10-11-12- 7 1 7-8-9-10-11-12-13-14 7-8-9-10-1121-22 7-8-9-10-11-12-13 ? ? ? ? ? ? 14 1 14-15-16-17-1828-29 14-15-16-17-18-19-20- 15 1 15-16-17-18-1929-30 15-16-17-18-19-20-21- clock edge the clock edge (ce) bit selects either a r ising (default) or falling clock edge for clk. this clock edge is used at the star t of a burst cy cle to output synchr onous data and to asser t/de-asser t w ait . burst w rap the burst wr ap (b w ) bit deter mines whether 4-wor d, 8-wor d, or 16-wor d burst length accesses wr ap within the selected wor d length boundar ies or cr oss wor d length boun- dar ies . when b w is set, burst wr apping does not occur (default). when b w is clear ed, burst wr apping occurs . when per for ming synchr onous burst r eads with b w set (no wr ap), an output delay may occur when the burst sequence cr osses its first device r o w (16-wor d) boundar y . i f the burst sequences star t addr ess is 4-wor d aligned, then no delay occurs . i f the star t ad- dr ess is at the end of a 4-wor d boundar y , the worst-case output delay is one clock cy cle less than the first access latency count. this delay can take place only once and doesnt occur if the burst sequence does not cr oss a device r o w boundar y . w ait infor ms the system of this delay when it occurs . burst length the burst length bits (bl[2:0]) select the linear burst length for all synchr onous burst r eads of the flash memor y arr ay . the burst lengths ar e 4-wor d, 8-wor d, 16-wor d, or con- tinuous . c ontinuous burst accesses ar e linear only and do not wr ap within any wor d length boundaries. when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the burstable address space. 512mb, 1gb, 2gb: p30-65nm configuration register pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 44 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
one-time pr ogrammable registers read otp registers the device contains 17 o tp r egisters that can be used to implement system secur ity measur es and/or device identification. each o tp r egister can be individually locked. the first 128-bit o tp r egister is compr ised of two 64-bit (8-wor d) segments . the lo w er 64-bit segment is pr epr ogr ammed at the m icr on factor y with a unique 64-bit number . the upper 64-bit segment, as w ell as the other sixteen 128-bit o tp r egisters , ar e blank. u sers can pr ogr am them as needed. o nce pr ogr ammed, users can also lock the o tp r egister(s) to pr ev ent additional bit pr ogr amming (see the o tp r egister m ap figur e be- lo w). the o tp r egisters contain o tp bits; when pr ogr ammed, pr bits cannot be er ased. each o tp r egister can be accessed multiple times to pr ogr am individual bits , as long as the r egister r emains unlocked. each o tp r egister has an associated lock r egister bit. when a lock r egister bit is pr o- gr ammed, the associated o tp r egister can only be r ead; it can no longer be pr ogr am- med. a dditionally , because the lock r egister bits themselv es ar e o tp , when pr ogr am- med, they cannot be er ased. ther efor e , when an o tp r egister is locked, it cannot be un- locked. the o tp r egisters can be r ead fr om an o tp -ra addr ess . t o r ead the o tp r egister , a read de vice identifier command is issued at an o tp -ra addr ess to place the de- vice in the read device identifier state. next, a read operation is performed using the address offset corresponding to the register to be read. the device identifier informa- tion table shows the address offsets of the otp registers and lock registers. pr data is read 16 bits at a time. 512mb, 1gb, 2gb: p30-65nm one-time programmable registers pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 45 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 13: otp register map 0 x 8 9 lock register 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 x 10 2 0 x 10 9 0 x 8 a 0 x 9 1 0 x 8 8 0 x 8 5 64-bit segment 64-bit segment lock register 0 register 0 128-bit otp register 1 128-bit otp 0 x 8 4 0 x 8 1 0 x 8 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 register 16 128-bit otp factory programed user programmable user programmable user programmable pr ogram otp registers t o pr ogr am an o tp r egister , a pr ogram o tp register command is issued at the pa- r ameters base addr ess plus the offset of the desir ed o tp r egister location. n ext, the de- sir ed o tp r egister data is wr itten to the same o tp r egister addr ess . the device pr ogr ams the 64-bit and 128-bit user -pr ogr ammable o tp r egister data 16 bits at a time . i ssuing the pr ogram o tp register command outside of the o tp r eg- isters addr ess space causes a pr ogr am err or (sr4 set). a ttempting to pr ogr am a locked o tp r egister causes a pr ogr am err or (sr4 set) and a lock err or (sr1 set). lock otp registers each o tp r egister can be locked b y pr ogr amming its r espectiv e lock bit in the lock r egis- ter . the corr esponding bit in the lock r egister is pr ogr ammed b y issuing the pr ogram l ock register command, follo w ed b y the desir ed lock r egister data. the physical ad- dr esses of the lock r egisters ar e 0x80 for r egister 0 and 0x89 for r egister 1; these addr ess- es ar e used when pr ogr amming the lock r egisters . bit 0 of lock register 0 is programmed during the manufacturing process, locking the lower-half segment of the first 128-bit otp register. bit 1 of lock register 0, which corre- sponds to the upper-half segment of the first 128-bit otp register, can be programmed by the user . when programming bit 1 of lock register 0, all other bits need to be left as 1 such that the data programmed is 0xfffd. 512mb, 1gb, 2gb: p30-65nm one-time programmable registers pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 46 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
lock r egister 1 contr ols the the upper sixteen 128-bit o tp r egisters . each bit of lock r eg- ister 1 corr esponds to a specific 128-bit o tp r egister . p r ogr amming a bit in lock r egister 1 locks the corr esponding 128-bit o tp r egister ; e .g., pr ogr amming lr1.0 locks the corr e- sponding o tp r egister 1. note: once locked, the otp registers cannot be unlocked. 512mb, 1gb, 2gb: p30-65nm one-time programmable registers pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 47 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
common flash interface the cfi is par t of an o v er all specification for multiple command-set and contr ol-inter - face descr iptions . s ystem softwar e can parse the cfi database str uctur e to obtain infor - mation about the device , such as block siz e , density , bus width, and electr ical specifica- tions . the system softwar e deter mines which command set to use to pr operly per for m a write command, a bl ock erase or read command, and to other wise contr ol the device . i nfor mation in the cfi database can be view ed b y issuing the read cfi com- mand. read cfi structur e output the read cfi command obtains cfi database str uctur e infor mation and always out- puts it on the lo w er b yte , dq[7:0], for a wor d-wide (x16) device . this cfi-compliant de- vice always outputs 00h data on the upper b yte (dq[15:8]). the numer ical offset v alue is the addr ess r elativ e to the maximum bus width the device suppor ts . f or this device family , the star ting addr ess is a 10h, which is a wor d addr ess for x16 devices . f or example , at this star ting addr ess of 10h, a read cfi command out- puts an ascii q in the lo w er b yte and 00h in the higher b yte as sho wn her e . i n all the cfi tables sho wn her e , addr ess and data ar e r epr esented in hexadecimal nota- tion. in addition, because the upper byte of word-wide devices is always 00h, as shown in the example here, the leading 00 has been dropped and only the lower byte value is shown. following is a table showing the cfi output for a x16 device, beginning at ad- dress 10h and a table showing an overview of the cfi database sections with their ad- dresses. table 17: example of cfi output (x16 device) as a function of device and mode device hex offset hex code ascii value (dq[15:8]) ascii value (dq[7:0]) address 00010: 51 00 q 00011: 52 00 r 00012: 59 00 y 00013: p_id lo 00 primary vendor id 00014: p_id hi 00 00015: p lo 00 primary vendor table address 00016: p hi 00 00017: a_id lo 00 alternate vendor id 00018: a_id hi 00 : : : : : : : : 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 48 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 18: cfi database: addresses and sections address section name description 00001:fh reserved reserved for vendor-specific information 00010h cfi id string flash device command set id (identification) and vendor da- ta offset 0001bh system interface information flash device timing and voltage 00027h device geometry definition flash device layout p primary micron-specific extended query vendor-defined informaton specific to the primary vendor algorithm (offset 15 defines p which points to the primary micron-specific extended query table.) table 19: cfi id string hex offset length description address hex code ascii value (dq[7:0]) 10h 3 query unique ascii string qry 10: - -51 q 11: - -52 r 12: - -59 y 13h 2 primary vendor command set and control interface id code. 16-bit id code for ven- dor-specified algorithms. 13: - -01 primary vendor id number 14: - -00 15h 2 extended query table primary algorithm address. 15: - -0a primary vendor table ad- dress, primary algorithm 16: - -01 17h 2 alternate vendor command set and control interface id code. 0000h means no second vendor-specified algorithm exists. 17: - -00 alternate vendor id number 18: - -00 19h 2 secondary algorithm extended query table address. 0000h means none exists. 19: - -00 primary vendor table ad- dress, secondary algorithm 1a: - -00 note: 1. the cfi id string provides verification that the device supports the cfi specification. it also indicates the specification version and supported vendor-specific command sets. 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 49 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 20: system interface information hex offset length description address hex code ascii value (dq[7:0]) 1bh 1 v cc logic supply minimum program/erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 bcd volts 1bh - -17 1.7v 1ch 1 v cc logic supply maximum program/erase volt- age. bits 0 - 3 bcd 100 mv bits 4 - 7 bcd volts 1ch - -20 2.0v 1dh 1 v pp [programming] supply minimum program/ erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 hex volts 1dh - -85 8.5v 1eh 1 v pp [programming] supply maximum program/ erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 hex volts 1eh - -95 9.5v 1fh 1 n such that typical single word program time- out = 2 n s. 1fh - -09 512s 20h 1 n such that typical full buffer write timeout = 2 n s. 20h - -0a 1024s 21h 1 n such that typical block erase timeout = 2 n ms. 21h - -0a 1s 22h 1 n such that typical full chip erase timeout = 2 n ms. 22h - -00 na 23h 1 n such that maximum word program timeout = 2 n times typical. 23h - -01 1024s 24h 1 n such that maximum buffer write timeout = 2 n times typical. 24h - -02 4096s 25h 1 n such that maximum block erase timeout = 2 n times typical. 25h - -02 4s 26h 1 n such that maximum chip erase timeout = 2 n times typical. 26h - -00 na 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 50 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 21: device geometry hex offset length description address hex code ascii value (dq[7:0]) 27h 1 n such that device size in bytes = 2 n . 27: see note 1 28h 2 flash device interface code assignment: n such that n + 1 specifies the bit field that represents the flash device width capabilities as described here: bit 0: x8 bit 1: x16 bit 2: x32 bit 3: x64 bits 4 - 7: C bits 8 - 15: C 28: - -01 x16 29: - -00 2ah 2 n such that maximum number of bytes in write buffer = 2 n . 2ah - -0a 1024 2bh - -00 2ch 1 number of erase block regions (x) within the device: 1) x = 0 means no erase blocking; the device erases in bulk. 2) x specifies the number of device regions with one or more contiguous, same-size erase blocks. 3) symmetrically blocked partitions have one blocking region. 2ch see note 1 2dh 4 erase block region 1 information: bits 0 - 15 = y , y + 1 = number of identical-size erase blocks. bits 16 - 31 = z, region erase block(s) size are z x 256 bytes. 2d: 2e: 2f: 30: see note 1 31h 4 erase block region 2 information: bits 0 - 15 = y , y + 1 = number of identical-size erase blocks. bits 16 - 31 = z, region erase block(s) size are z x 256 bytes. 31: 32: 33: 34: see note 1 35h 4 reserved for future erase block region information. 35: 36: 37: 38: see note 1 note: 1. see block region map information table. table 22: block region map information address 512mb 1gb 2gb top bottom symmetrical top bottom symmetrical symmetrical 27: --1a --1a --1a --1b --1b --1b --1b 28: --01 --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 --00 2a: --0a --0a --0a --0a --0a --0a --0a 2b: --00 --00 --00 --00 --00 --00 --00 2c: --02 --02 --01 --02 --02 --01 --01 2d: --fe --03 --ff --fe --03 --ff --ff 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 51 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 22: block region map information (continued) address 512mb 1gb 2gb top bottom symmetrical top bottom symmetrical symmetrical 2e: --01 --00 --01 --03 --00 --03 --03 2f: --00 --80 --00 --00 --80 --00 --00 30: --02 --00 --02 --02 --00 --02 --02 31: --03 --fe --00 --03 --fe --00 --00 32: --00 --01 --00 --00 --03 --00 --00 33: --80 --00 --00 --80 --00 --00 34: --00 --02 --00 --00 --02 --00 35:~38: --00 --00 --00 --00 --00 --00 table 23: primary vendor-specific extended query hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+0)h (p+1)h (p+2)h 3 primary extended query table, unique ascii string: pri 10a: - -50 p 10b: - -52 r 10c: - -49 i (p+3)h 1 major version number, ascii 10d: - -31 1 (p+4)h 1 minor version number, ascii 10e: - -35 5 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 52 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 23: primary vendor-specific extended query (continued) hex of fset p = 10ah length description address hex code ascii value (dq[7:0]) (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support (1 = yes; 0 = no) bits 11 - 29 are reserved; undefined bits are 0 if bit 31 = 1, then another 31-bit field of optional features follows at the end of the bit 30 field. 10f: - -e6 C 110: - -01 C 111: - -00 C 112: see note 1 C bit 0: chip erase supported. bit 0 = 0 no bit 1: suspend erase supported. bit 1 = 1 yes bit 2: suspend program supported. bit 2 = 1 yes bit 3: legacy lock/unlock supported. bit 3 = 0 no bit 4: queued erase supported. bit 4 = 0 no bit 5: instant individual block locking supported. bit 5 = 1 yes bit 6: otp bits supported. bit 6 = 1 yes bit 7: page mode read supported. bit 7 = 1 yes bit 8: synchronous read supported. bit 8 = 1 yes bit 9: simultaneous operations supported. bit 9 = 0 no bit 10: extended flash array block supported. bit 10 = 0 no bit 11: permanent block locking of up to full main array supported. bit 11 = 0 yes bit 12: permanent block locking of up to partial main array supported. bit 12 = 0 no bit 30: cfi links to follow: bit 30 see note 1 bit 31: another optional features field to follow. bit 31 (p+9)h 1 supported functions after suspend: read ar- ra y , st a tus, quer y . other supported options in- clude: bits 1 - 7: reserved; undefined bits are 0. 113: - -01 C bit 0: program supported after erase suspend. bit 0 = 1 yes (p+a)h (p+b)h 2 block status register mask: bits 2 - 15 are reserved; undefined bits are 0. 114: - -03 C 115: - -00 C bit 0: block lock-bit status register active. bit 0 = 1 yes bit 1: block lock-down bit status active. bit 1 = 1 yes bit 4: efa block lock-bit status register active. bit 4 = 0 no bit 5: efa block lock-bit status active. bit 5 = 0 no (p+c)h 1 v cc logic supply highest performance program/ erase voltage. bits 0 - 3 bcd 100 mv bits 4 - 7 hex value in volts 116: - -18 1.8v 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 53 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 23: primary vendor-specific extended query (continued) hex of fset p = 10ah length description address hex code ascii value (dq[7:0]) (p+d)h 1 v pp optimum program/erase voltage. bits 0 - 3 bcd 100mv bits 4 - 7 hex value in volts 117: - -90 9.0v note: 1. see optional features fields table. table 24: optional features field address discrete 2gb bottom top bottom top C C die 1 (b) die 2 (t) die 1 (t) die 2 (b) 112: --00 --00 40: --00 --40 --00 table 25: one time programmable (otp) space information hex of fset p = 10ah length description address hex code ascii value (dq[7:0]) (p+e)h 1 number of otp block fields in jedec id space. 00h indicates that 256 otp fields are available. 118: - -02 2 (p+f)h (p+10)h (p+11)h (p+12)h 4 otp field 1: otp description: this field describes user -available otp bytes. some are preprogrammed with device-unique se- rial numbers. others are user -programmable. bits 0-15 point to the otp lock byte (the first byte). the following bytes are factory preprogrammed and user -programmable: bits 0 - 7 = lock/bytes jedec plane physical low address. bits 8 - 15 = lock/bytes jedec plane physical high address. bits 16 - 23 = n where 2 n equals factory preprog- rammed bytes. bits 24 - 31 = n where 2 n equals user-programma- ble bytes. 119: - -80 80h 11a: - -00 00h 1b: - -03 8 byte 11c: - -03 8 byte 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 54 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 25: one time programmable (otp) space information (continued) hex of fset p = 10ah length description address hex code ascii value (dq[7:0]) (p+13)h (p+14)h (p+15)h (p+16)h 10 protection field 2: protection description bits 0 - 31 point to the protection register physi- cal lock word address in the jedec plane. the bytes that follow are factory or user-progam- mable. 11d: - -89 89h 11e: - -00 00h 11f: - -00 00h 120: - -00 00h (p+17)h (p+18)h (p+19)h bits 32 - 39 = n where n equals factory program- med groups (low byte). bits 40 - 47 = n where n equals factory program- med groups (high byte). bits 48 - 55 = n where 2n equals factory program- med bytes/groups. 121: - -00 0 122: - -00 0 123: - -00 0 (p+1a)h (p+1b)h (p+1c)h bits 56 - 63 = n where n equals user programmed groups (low byte). bits 64 - 71 = n where n equals user programmed groups (high byte). bits 72 - 79 = n where 2 n equals user programma- ble bytes/groups. 124: - -10 16 125: - -00 0 126: - -04 16 table 26: burst read information hex of fset p = 10ah length description address hex code ascii value (dq[7:0]) (p+1d)h 1 page mode read capability: bits 7 - 0 = n where 2 n hex value represents the number of read-page bytes. see of fset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. 127: - -05 32 byte (p+1e)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capabili- ty. 128: - -04 4 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 55 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 26: burst read information (continued) hex offset p = 10ah length description address hex code ascii value (dq[7:0]) (p+1f)h 1 synchronous mode read capability configuration 1: bits 3 - 7 = reserved. bits 0 - 2 = n where 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maxi- mum word width. a value of 07h indicates that the device is capa- ble of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fieldss 3-bit value can be written directly to the read configuration register bits 0 - 2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 129: - -01 4 (p+20)h 1 synchronous mode read capability configuration 2. 12a: - -02 8 (p+21)h 1 synchronous mode read capability configuration 3. 12b: - -03 16 (p+22) 1 synchronous mode read capability configuration 4. 12c: - -07 continued table 27: partition and block erase region information hex of fset p = 10ah description optional flash features and commands length address bottom top bottom top (p+23)h (p+23)h number of device hardware-partition regions within the device: x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions 1 12d: 12d: 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 56 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 28: partition region 1 information: top and bottom offset/address hex of fset p = 10ah description optional flash features and commands length address bottom top bottom top (p+24)h (p+25)h (p+24)h (p+25)h data size of this partition region information field (number of addressable locations, including this field. 2 12e: 12e: 12f: 12f: (p+26)h (p+27)h (p+26)h (p+27)h number of identical partitions within the partition region. 2 130: 130: 131: 131: (p+28)h (p+28)h number of program or erase operations allowed in a partition: bits 0 - 3 = number of simultaneous program opera- tions. bits 4 - 7 = number of simultaneous erase operations. 1 132: 132: (p+29)h (p+29)h simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode: bits 0 - 3 = number of simultaneous program opera- tions. bits 4 - 7 = number of simultaneous erase operations. 1 133: 133: (p+2a)h (p+2a)h simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode: bits 0 - 3 = number of simultaneous program opera- tions. bits 4 - 7 = number of simultaneous erase operations. 1 134: 134: (p+2b)h (p+2b)h t ypes of erase block regions in this partition region: x=0: no erase blocking; the partition region erases in bulk. x = number of erase block regions with contiguous, same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (t ype 1 blocks) x (t ype 1 block sizes) + (type 2 blocks) x (type 2 block sizes) +...+ (type n blocks) x (type n block sizes). 1 135: 135: table 29: partition region 1 information hex of fset p = 10ah bottom/top description optional flash features and commands length address bottom/top (p+2c)h (p+2d)h (p+2e)h (p+2f)h partition region 1 erase block type 1 information: bits 0-15 = y , y+1 = number of identical-sized erase blocks in a partition. bits 16-31 = z, where region erase block(s) size is z x 256 bytes. 4 136: 137: 138: 139: 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 57 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 29: partition region 1 information (continued) hex of fset p = 10ah bottom/top description optional flash features and commands length address bottom/top (p+30)h (p+31)h partition 1 (erase block type 1): minimum block erase cycles x 1000 2 13a: 13b: (p+32)h partition 1 (erase block type 1) bits per cell; internal ecc: bits 0 - 3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bit 5 - 7 = reserved for future use 1 13c: (p+33)h partition 1 (erase block type 1) page mode and synchronous mode capabilities: bits 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bit 3 - 7 = reserved for future use 1 13d: (p+34)h (p+35)h (p+36)h (p+37)h (p+38)h (p+39)h partition 1 (erase block type 1) programming region information: bits 0 - 7 = x, 2 x : programming region aligned size (bytes) bit 8-14 = reserved for future use bit 15 = legacy flash operation; ignore 0:7 bit 16 - 23 = y: control mode valid size (bytes) bit 24 - 31 = reserved for future use bit 32 - 39 = z: control mode invalid size (bytes) bit 40 - 46 = reserved for future use bit 47 = legacy flash operation (ignore 23:16 and 39:32) 6 13e: 13f: 140: 141: 142: 143: (p+3a)h (p+3b)h (p+3c)h (p+3d)h partition 1 erase block type 2 information: bits 0-15 = y , y+1 = number of identical-size erase blocks in a par - tition. bits 16 - 31 = z, where region erase block(s) size is z x 256 bytes. (bottom parameter device only) 4 144: 145: 146: 147: (p+3e)h (p+3f)h partition 1 (erase block type 2) minimum block erase cycles x 1000 2 148: 149: (p+40)h partition 1 (erase block type 2) bits per cell, internal edac: bits 0 - 3 = bits per cell in erase region bit 4 = reserved for internal ecc used (1=yes, 0=no) bits 5 - 7 = reserved for future use 1 14a: (p+41)h partition 1 (erase block type 2) page mode and synchronous mode capabilities: bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use 1 14b: 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 58 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 29: partition region 1 information (continued) hex of fset p = 10ah bottom/top description optional flash features and commands length address bottom/top (p+42)h (p+43)h (p+44)h (p+45)h (p+46)h (p+47)h partition 1 (erase block type 2) programming region information: bits 0-7 = x, 2 n x = programming region aligned size (bytes) bits 8-14 = reserved for future use bit 15 = legacy flash operation (ignore 0:7) bits 16 - 23 = y = control mode valid size in bytes bits 24 - 31 = reserved bits 32 - 39 = z = control mode invalid size in bytes bits 40 - 46 = reserved bit 47 = legacy flash operation (ignore 23:16 and 39:32) 6 14c: 14d: 14e: 14f: 150: 151: 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 59 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 30: partition region 1: partition and erase block map information add. 512mb 1gb 2gb top bottom symm. top bottom symm. symm. upper die symm. lower die 12d: --01 --01 --01 --01 --01 --01 --01 --01 12e: --24 --24 --14 --24 --24 --14 --14 --14 12f: --00 --00 --00 --00 --00 --00 --00 --00 130: --01 --01 --01 --01 --01 --01 --01 --01 131: --00 --00 --00 --00 --00 --00 --00 --00 132: --11 --11 --11 --11 --11 --11 --11 --11 133: --00 --00 --00 --00 --00 --00 --00 --00 134: --00 --00 --00 --00 --00 --00 --00 --00 135: --02 --02 --01 --02 --02 --01 --01 --01 136: --fe --03 --ff --fe --03 --ff --ff --ff 137: --01 --00 --01 --03 --00 --03 --03 --03 138: --00 --80 --00 --00 --80 --00 --00 --00 139: --02 --00 --02 --02 --00 --02 --02 --02 13a: --64 --64 --64 --64 --64 --64 --64 --64 13b: --00 --00 --00 --00 --00 --00 --00 --00 13c: --02 --02 --02 --02 --02 --02 --02 --02 13d*: --03 --03 --03 --03 --03 --03 --03 --03 13e: --00 --00 --00 --00 --00 --00 --00 --00 13f: --80 --80 --80 --80 --80 --80 --80 --80 140: --00 --00 --00 --00 --00 --00 --00 --00 141: --00 --00 --00 --00 --00 --00 --00 --00 142: --00 --00 --00 --00 --00 --00 --00 --00 143: --80 --80 --80 --80 --80 --80 --80 --80 144: --03 --fe --ff --03 --fe --ff --ff --10 145: --00 --01 --ff --00 --03 --ff --ff --c8 146: --80 --00 --ff --80 --00 --ff --ff --00 147: --00 --02 --ff --00 --02 --ff --ff --00 148: --64 --64 --ff --64 --64 --ff --ff --10 149: --00 --00 --ff --00 --00 --ff --ff --ff 14a: --02 --02 --ff --02 --02 --ff --ff --ff 14b: --03 --03 --ff --03 --03 --ff --ff --ff 14c: --00 --00 --ff --00 --00 --ff --ff --ff 14d: --80 --80 --ff --80 --80 --ff --ff --ff 14e: --00 --00 --ff --00 --00 --ff --ff --ff 14f: --00 --00 --ff --00 --00 --ff --ff --ff 150: --00 --00 --ff --00 --00 --ff --ff --ff 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 60 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 30: partition region 1: partition and erase block map information (continued) add. 512mb 1gb 2gb top bottom symm. top bottom symm. symm. upper die symm. lower die 151: --80 --80 --ff --80 --80 --ff --ff --ff table 31: cfi link information C 2gb length description address ascii value (dq[7:0]) 4 cfi link field bit definitions: bits 0 - 9 = address of fset (within 32mb segment of referenced cfi table) bits 10 - 27 = nth 32mb segment of referenced cfi table bits 28 - 30 = memory t ype bit 31 = another cfi link field immediately follows 144: 145: 146: 147 see note 1 1 cfi link field quantity subfield definitions: bits 0 - 3 = quantity field (n such that n+1 equals quantity) bit 4 = t able and die relative location bit 5 = link field and table relative location bits 6 - 7 = reserved 148: note: 1. see "partition region 1: partition and erase block map information" table. 512mb, 1gb, 2gb: p30-65nm common flash interface pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 61 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
flowcharts figur e 14: w or d pr ogram pr ocedur e no progam complete d7 = 1? command cycle - issue program command - address = location to program - data = 0x40 start program suspend (see suspend/resume flowchart yes yes yes no no suspend? data cycle - address = location to program - data = data to program check ready status - read status register command not required - perform read operation - read ready status on signal d7 errors? read status register - toggle ce# or oe# to update status register - see status register flowchart error-handler user-defined routine 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 62 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 15: buf fer pr ogram pr ocedur e yes device ready? sr7 = 0/1 set timeout or loop counter start use single word programming get next target address read status register sr7 = valid (at block address ) timeout or count expired? issue write-to-buffer command e8h (at block address) x = 0 write confirm d0h (at block address) (at block address) read status register device supports buffer writes? write word count (n-1) (at block address) write buffer data, start address write buffer data, (at block address) within buffer range x = x + 1 no no 0 = no no yes yes no yes 1 = yes x = n abort bufferred program ? 0 full status check (if desired) 1 sr7? suspend program no another buffered programming ? program complete write to another block address suspend program loop buffered program aborted yes 1 = ready 0 = busy n = 0 corresponds to count = 1 ce# and oe# low updates status register no yes notes: 1. w ord count values on dq0:dq15 are loaded into the count register . count ranges for this device are n = 0000h to 01ffh. 2. device outputs the status register when read. 3. w rite buf fer contents will be programmed at the device start or destination address. 4. align the start address on a write buf fer boundary for maximum programming perform- ance; that is, a[9:1] of the start address = 0). 5. device aborts the buffered program command if the current address is outside the original block address. 6. status register indicates an improper command sequence if the buffered program command is aborted. follow this with a clear st a tus register command. 7. device defaults to sr output data after buffered programming setup command (e8h) is issued . ce# or oe# must be toggled to update the status register . dont issue the read sr command (70h); it is interpreted by the device as buf fer word count. 8. full status check can be done after erase and write sequences complete. w rite ffh after the last operation to reset the device to read array mode. 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 63 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 16: buf fer ed enhanced factory pr ogramming (befp) pr ocedur e no (sr7 = 1) yes (sr7 = 0) yes (sr0 = 0) befp setup done? issue befp setup data = 0x80 start exit issue befp confirm data = 00d0h befp setup delay read status register sr error-handler user-defined yes no buffer full? buffer ready? read status register register write data word to buffer read status register program done? no yes program more data ? write 0xffff outside block setup phase program and verify phase exit phase finish yes (sr7 = 1) no (sr7 = 0) befp exited? full status register check for errors no (sr0 = 1) no (sr0 = 1) yes (sr0 = 0) read status 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 64 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 17: block erase pr ocedur e start sr7 = 1? erase suspend see suspend/ resume flowchart error handler user-defined routine end command cycle - issue erase command - address = block to be erased - data = 0x20 yes yes no no suspend? confirm cycle check ready status - issue confirm command - address = block to be erased - data = erase confirm (0xd0) - read status register command not required - perform read operation - read ready status on sr7 no yes errors? read status register - toggle ce# or oe# to update status register - see status register flowchart 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 65 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 18: pr ogram suspend/resume pr ocedur e read status register = sr2 sr7 = read array data program completed done reading program resumed read array data 0 no 0 yes 1 1 start write b0h any address program suspend read status write 70h write ffh any address read array write d0h any address program resume write ffh read array write 70h any address read status any address 1 = ready 0 = busy 1 = suspended 0 = completed (address = block to suspend) update the status register initiate read cycle to from a block other than programmed from the one being 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 66 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 19: erase suspend/resume pr ocedur e read status register = sr6 sr7 = read/program? erase completed done? erase resumed read array data 0 0 yes no 1 1 start write b0h any address erase suspend read status write 70h write d0h any address erase resume write ffh read array write 70h any address read status any address 1 = suspended 0 = completed 1 = ready 0 = busy (ffh/40h) address = x toggle ce#/oe# to update the status register read program read array data from a block other than the one being erased program loop: to a block other than the one being erased 1 note: 1. the t ers/susp timing between the initial block erase or erase resume command and a subsequent erase suspend command should be followed. 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 67 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 20: block lock operations pr ocedur e write 90h read block lock status locking change? lock change complete no yes start write 01h, d0h, 2fh block address lock confirm read id plane lock setup write 60h write ffh any address read array block address optional 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 68 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 21: otp register pr ogramming pr ocedur e start sr7 = 1? end otp program setup - write 0xc0 - otp address yes no confirm data - write otp address and data check ready status - read st a tus register command not required - perform read operation - read ready status on sr7 read status register - t oggle ce# or oe# to update status register - see status register flowchart 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 69 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 22: status register pr ocedur e erase suspend see suspend/ resume flowchart set/reset by device - set by device - reset by user - see clear status register command start end command cycle - issue status register command - address = any device address - data = 0x70 data cycle - read status register sr[7:0] yes yes yes no no no yes yes no no sr7 = 1 sr6 = 1 sr2 = 1 sr5 = 1 sr4 = 1 sr4 = 1 sr3 = 1 sr1 = 1 no yes yes yes no no program suspend see suspend/ resume flowchart error erase failure error command sequence error program failure error v pen /v pp < v penlk /v pplk error block locked 512mb, 1gb, 2gb: p30-65nm flowcharts pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 70 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
power and reset specifications v c c should attain v c cmin fr om v ss simultaneously with or befor e applying v c c q , v pp dur ing po w er up . v c c should attain v ss dur ing po w er do wn. d evice inputs should not be dr iv en befor e supply v oltage = v c cmin . p o w er supply tr ansitions should only occur when rst# is l o w . this pr otects the device fr om accidental pr ogr amming or er asur e dur ing po w er tr ansitions . asser ting rst# dur ing a system r eset is impor tant with automated pr ogr am/er ase devi- ces because systems typically expect to r ead fr om the device when coming out of r eset. i f a cpu r eset occurs without a device r eset, pr oper cpu initialization may not occur . this is because the device may be providing status information, instead of array data as expected. connect rst# to the same active low reset signal used for cpu initialization. because the device is disabled when rst# is asserted, it ignores its control inputs dur- ing power-up/down. invalid bus conditions are masked, providing a level of memory protection. table 32: power and reset parameter symbol min max unit notes rst# pulse width low t plph 100 C ns 1, 2, 3, 4 rst# low to device reset during erase t plph C 25 us 1, 3, 4, 7 rst# low to device reset during program C 25 1, 3, 4, 7 v cc power valid to rst# de-assertion (high) t vccph 300 C 1, 4, 5, 6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to v cc . 4. sampled, but not 100% tested. 5. when rst# is tied to the v cc supply , device will not be ready until t vccph after v cc v ccmin . 6. when rst# is tied to the v ccq supply , device will not be ready until t vccph after v cc v ccmin . 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing. 512mb, 1gb, 2gb: p30-65nm power and reset specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 71 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 23: reset operation w aveforms (a) reset during read mode v ih v il rst# (d) v cc power-up to rst# high t plph t phqv t phqv t phqv v cc 0v v cc t vccph (b) reset during program or block erase p1 p2 v ih v il rst# abort complete abort complete t plrh (c) reset during program or block erase p1 p2 v ih v il rst# t plrh power supply decoupling the device r equir es car eful po w er supply de-coupling. thr ee basic po w er supply cur - r ent consider ations ar e 1) standb y curr ent lev els , 2) activ e curr ent lev els , and 3) tr ansi- ent peaks pr oduced when ce# and oe# ar e asser ted and de-asser ted. when the device is accessed, inter nal conditions change . cir cuits within the device ena- ble char ge pumps , and inter nal logic states change at high speed. these inter nal activi- ties pr oduce tr ansient signals . t r ansient curr ent magnitudes depend on the device out- puts capacitiv e and inductiv e loading. t wo-line contr ol and corr ect de-coupling capac- itor selection suppr ess tr ansient v oltage peaks . b ecause the devices dr aw their po w er fr om v c c , v pp , and v c c q , each po w er connection should hav e a 0.1f and a 0.01f cer amic capacitor to gr ound. h igh-fr equency , inher - ently lo w-inductance capacitors should be placed as close as possible to package leads . a dditionally , for ev er y eight devices used in the system, a 4.7f electr olytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. 512mb, 1gb, 2gb: p30-65nm power and reset specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 72 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
maximum ratings and operating conditions stresses greater than those listed can cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other condi- tions above those indicated is not guaranteed. table 33: maximum ratings parameter maximum rating notes temperature under bias C40c to + 85 c storage temperature C65c to + 125 c voltage on any signal (except v cc , v pp , and v ccq ) C2v to +5.6v 1 v pp voltage C2v to +11.5v 1, 2 v cc voltage C2v to +4v 1 v ccq voltage C2v to +5.6v 1 output short circuit current 100ma 3 notes: 1. v oltages shown are specified with respect to v ss . during infrequent nonperiodic transi- tions, the level may undershoot to C2v for periods less than 20ns or overshoot to v cc + 2v or v ccq + 2v or v pp + 2v for periods less than 20ns. 2. program/erase voltage is typically 1.7C2.0v . 9.0v can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0v program/erase voltage may reduce block cycling capability . 3. output is shorted for no more than one second, and more than one output is not shor- ted at one time. table 34: operating conditions symbol parameter min max unit notes t a operating temperature C40 +85 c 1 v cc v cc supply voltage 1.7 2.0 v v ccq i/o supply voltage cmos inputs 1.7 3.6 ttl inputs 2.4 3.6 v ppl v pp voltage supply (logic level) 0.9 3.6 2 v pph buffered enhanced factory programming v pp 8.5 9.5 t pph maximum v pp hours v pp = v pph C 80 hours block erase cycles array blocks v pp = v ppl 100,000 C cycles v pp = v pph C 1000 notes: 1. t a = ambient temperature. 2. in typical operation, v pp program voltage is v ppl . 512mb, 1gb, 2gb: p30-65nm maximum ratings and operating conditions pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 73 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
dc electrical specifications table 35: dc current characteristics parameter symbol cmos inputs (v ccq = 1.7C 3.6v) ttl inputs (v ccq = 2.4C 3.6v) unit test conditions notes typ max typ max input load current 512mb 1gb i li C 1 C 2 a v cc = v cc (max) v ccq = v ccq (max) v in = v ccq or v ss 1, 6 2gb C 2 C 4 output leakage current dq[15:0], wait 512mb 1gb i lo C 1 C 10 a v cc = v cc (max) v ccq = v ccq (max) v in = v ccq or v ss 2gb C 2 C 20 v cc standby, power-down 512mb i ccs , i ccd 70 225 70 225 a v cc = v cc (max) v ccq = v ccq (max) ce# = v ccq rst# = v ccq (for i ccs ) rst# = v ss (for i ccd ) wp# = v ih 1. 2 1gb 75 240 75 240 2gb 150 480 150 480 average v cc read current asynchronous single-word f = 5 mhz (1 clk) i ccr 26 31 26 31 ma 16-word read v cc = v cc (max) ce# = v il oe# = v ih inputs: v il or v ih 1 12 16 12 16 ma 16-word read 19 22 19 22 ma 8-word read page mode read f = 13 mhz (17 clk) 16 18 16 18 ma 16-word read synchronous burst f = 52 mhz, lc = 4 21 24 21 24 ma continuous read v cc program current, v cc erase current i ccw, i cce 35 50 35 50 ma v pp = v ppl , program/erase in progress 1, 3, 5 35 50 35 50 v pp = v pph , program/erase in progress 1, 3, 5 v cc program sus- pend current, v cc erase suspend current 512mb i ccws, i cces 70 225 70 225 a ce# = v ccq , suspend in progress 1, 3, 4 1gb 2gb 75 240 75 240 v pp standby current 512mb i pps 0.2 5 0.2 5 a v pp = v ppl , in standby mode 1, 3, 7 1gb 0.2 5 0.2 5 2gb 0.4 10 0.4 10 v pp program suspend current, v pp erase suspend current i ppws, i ppes 0.2 5 0.2 5 a v pp = v ppl , suspend in progress 1, 3, 7 v pp read i ppr 2 15 2 15 a v pp = v ppl 1, 3 v pp program current i ppw 0.05 0.1 0.05 0.1 ma v pp = v ppl , program in progress 3 0.05 0.1 0.05 0.1 v pp = v pph , program in progress 512mb, 1gb, 2gb: p30-65nm dc electrical specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 74 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 35: dc current characteristics (continued) parameter symbol cmos inputs (v ccq = 1.7C 3.6v) ttl inputs (v ccq = 2.4C 3.6v) unit test conditions notes typ max typ max v pp erase current i ppe 0.05 0.1 0.05 0.1 ma v pp = v ppl , erase in progress 3 0.05 0.1 0.05 0.1 v pp = v pph , erase in progress v pp blank check i ppbc 0.05 0.1 0.05 0.1 ma v pp = v ppl 3 0.05 0.1 0.05 0.1 v pp = v pph notes: 1. all currents are rms unless noted. t ypical values at typ v cc , t c = +25c. 2. i ccs is the average current measured over any 5ms time interval 5s after ce# is de-asser - ted. 3. sampled, not 100% tested. 4. i cces is specified with the device deselected. if device is read while in erase suspend, cur - rent is i cces plus i ccr . 5. i ccw , i cce measured over typ or max times specified in (page 0 ). 6. if v in > v cc , the input load current increases to 10a max. 7. the i pps, i ppws, i ppes will increase to 200a when v pp /wp# is at v pph . table 36: dc voltage characteristics parameter symbol cmos inputs (v ccq = 1.7C3.6v) ttl inputs 1 (v ccq = 2.4C3.6v) unit test conditions notes min max min max input low voltage v il C0.5 0.4 C0.5 0.6 v 2 input high voltage v ih v ccq - 0.4 v ccq + 0.5 2 v ccq + 0.5 v output low voltage v ol C 0.2 C 0.2 v v cc = v cc (min) v ccq = v ccq (min) i ol = 100a output high voltage v oh v ccq - 0.2 C v ccq C 0.2 C v v cc = v cc (min) v ccq = v ccq (min) i oh = C100a v pp lock out voltage v pplk C 0.4 C 0.4 v 3 notes: 1. synchronous read mode is not supported with ttl inputs. 2. v il can undershoot to C1.0v for durations of 2ns or less and v ih can overshoot to v ccq + 1.0v for durations of 2ns or less. 3. v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges. 512mb, 1gb, 2gb: p30-65nm dc electrical specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 75 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac t est conditions and capacitance figur e 24: ac input/output refer ence timing input v ccq /2 v ccq /2 output v ccq 0v test points note: 1. ac test inputs are driven at v ccq for logic 1 and at 0v for logic 0. input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) <5ns. w orst-case speed oc- curs at v cc = v cc (min). figur e 25: t ransient equivalent load cir cuit device under test out c l notes: 1. see the test configuration for worst-case speed conditions table for component values. 2. cl includes jig capacitance. table 37: test configuration: worst-case speed condition test configuration c l (pf) v ccq (min) standard test 30 figur e 26: clock input ac w aveform t fclk/rclk clk t ch/cl v ih v il t clk 512mb, 1gb, 2gb: p30-65nm ac test conditions and capacitance pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 76 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 38: capacitance parameter sym- bol signal density min typ max unit condition notes input capacitance c in address, data, ce#, we#, oe#, rst#, clk, adv#, wp# 512mb 3 7 8 pf typ temp = 25c; max temp = 85c v cc = 0C2.0v, v ccq = 0C 3.6v discrete silicon die 1 1gb 4 8 9 2gb 6 16 18 output capacitance c out data, wait 512mb 3 5 7 1gb 3 5 6 2gb 6 10 12 note: 1. sampled, but not 100% tested. 512mb, 1gb, 2gb: p30-65nm ac test conditions and capacitance pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 77 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac read specifications table 39: ac read specifications parameter symbol min max unit notes asynchronous specifications read cycle time t avav easy bga 512mb/1gb 100 C ns C 2gb 105 C tsop 512mb/1gb 110 C address to output valid t avqv easy bga 512mb/1gb C 100 ns C 2gb C 105 tsop 512mb/1gb C 110 ce# low to output valid t elqv easy bga 512mb/1gb C 100 ns C 2gb C 105 tsop 512mb/1gb C 110 ns C oe# low to output valid t glqv - 25 ns 1, 2 rst# high to output valid t phqv - 150 ns 1 ce# low to output in low-z t elqx 0 C ns 1, 3 oe# low to output in low-z t glqx 0 C ns 1, 2, 3 ce# high to output in high-z t ehqz C 20 ns 1, 3 oe# high to output in high-z t ghqz C 15 ns output hold from first occur - ring address, ce#, or oe# change t oh 0 C ns ce# pulse width high t ehel 17 C ns 1 ce# low to wait valid t eltv C 17 ns ce# high to wait high-z t ehtz C 20 ns 1, 3 oe# low to wait valid t gltv C 17 ns 1 oe# low to wait in low-z t gltx 0 C ns 1, 3 oe# high to wait in high-z t ghtz C 20 ns latching specifications (easy bga) address setup to adv# high t avvh 10 C ns 1 ce# low to adv# high t elvh 10 C ns adv# low to output valid t vlqv easy bga 512mb/1gb C 100 ns 2gb C 105 tsop 512mb/1gb C 110 ns adv# pulse width low t vlvh 10 C ns adv# pulse width high t vhvl 10 C ns address hold from adv# high t vhax 9 C ns 1, 4 page address access t apa C 25 ns 1 rst# high to adv# high t phvh 30 - ns clock specifications (easy bga) 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 78 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 39: ac read specifications (continued) parameter symbol min max unit notes clk frequency t clk C 52 mhz 1, 3, 5, 6 clk period t clk 19.2 C ns clk high/low time t ch/cl 5 C ns clk fall/rise time t fclk/rclk 0.3 3 ns synchronous specifications (easy bga) 5 address setup to clk t avch/l 9 C ns 1, 6 adv# low setup to clk t vlch/l 9 C ns ce# low setup to clk t elch/l 9 C ns clk to output valid t chqv / t clqv C 17 ns output hold from clk t chqx 3 - ns 1, 6 address hold from clk t chax 10 - ns 1, 4, 6 clk to wait valid t chtv C 17 ns 1, 6 clk valid to adv# setup t chvl 3 C ns 1 wait hold from clk t chtx 3 C ns 1, 6 notes: 1. see ac t est conditions for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv C t glqv after ce#s falling edge without impact to t elqv . 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax, whichever timing specifica- tion is satisfied first. 5. synchronous read mode is not supported with ttl level inputs. 6. applies only to subsequent synchronous reads. 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 79 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 27: asynchr onous single-w or d read (adv# low) a t ava v adv# ce# oe# w ait dq rst# t a vqv t elqv t glqv t g l tv t glqx t elqx t phqv t ehqz t ghqz t ghtz note: 1. w ait shown deasserted during asynchronous read mode (rcr10 = 0, w ait asserted low). figur e 28: asynchr onous single-w or d read (adv# latch) a[4:1] a[max:5] ce# oe# wait dq adv# t elqx t glqv t elqv t ehqz t ghqz t ghtz t oh t avav t avqv t vhvl t avvh t gltv t glqx t vhax note: 1. wait shown deasserted during asynchronous read mode (rcr10 = 0, wait asserted low). 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 80 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 29: asynchr onous page mode read a[max:5] a[4:1] adv# t avqv t vhax t vhvl t avvh ce# oe# wait dq t ehtz t oh t oh t oh t apa t elqx t apa t apa t elqv t glqv valid address 1 0 2 f q1 q2 q3 q16 t oh t ehqz t ghqz note: 1. wait shown deasserted during asynchronous read mode (rcr10 = 0, wait asserted low). 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 81 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 30: synchr onous single-w or d array or nonarray read clk ce# oe# w ait dq adv# a t a vch t chax t a vqv t a vvh t v l vh t elch t e l vh t elqv t glqx t gltx t ghqz t ehqz t chtx t glqv t chqv t chqx t ghtz t chtv t vhax t vhvl notes: 1. w ait is driven per oe# assertion during synchronous array or nonarray read and can be configured to assert either during or one data cycle before valid data. 2. in this example, an n -word burst is initiated to the flash memory array and is terminated by ce# deassertion after the first word in the burst. 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 82 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 31: continuous burst read with output delay a clk adv# ce# oe# wait dq t vlch t avch t avvh t avqv t chax t chqv t chqv t chqv t chtx t chtv t chqv t glqx t glqv t elch t chqx t chqx t chqx t chqx t elvh t elqv t gltx t vhvl t vhax notes: 1. w ait is driven per oe# assertion during synchronous array or nonarray read and can be configured to assert either during or one data cycle before valid data. 2. at the end of a wordline; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 83 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 32: synchr onous burst mode 4-w or d read a clk adv# ce# oe# wait dq t vlch t avch latency count t avvh t avqv t chax t ghtz t chtv t ghqz t chqv t chqv t glqx t glqv t oh t chqx t elvh t elqv t gltv t vhvl t vhax a t elch t ehqz q0 q1 q2 q3 note: 1. w ait is driven per oe# assertion during synchronous array or nonarray read. w ait as- serted during initial latency and deasserted during valid data (rcr10 = 0, wait asserted low). 512mb, 1gb, 2gb: p30-65nm ac read specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 84 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac write specifications table 40: ac write specifications parameter symbol min max unit notes rst# high recovery to we# low t phwl 150 - ns 1, 2, 3 ce# setup to we# low t elwl 0 - ns 1, 2, 3 we# write pulse width low t wlwh 50 - ns 1, 2, 4 data setup to we# high t dvwh 50 - ns 1, 2, 12 address setup to we# high t avwh 50 - ns 1, 2 ce# hold from we# high t wheh 0 - ns data hold from we# high t whdx 0 - ns address hold from we# high t whax 0 - ns we# pulse width high t whwl 20 - ns 1, 2, 5 v pp setup to we# high t vpwh 200 - ns 1, 2, 3, 7 v pp hold from status read t qvvl 0 - ns wp# hold from status read t qvbl 0 - ns 1, 2, 3, 7 wp# setup to we# high t bhwh 200 - ns we# high to oe# low t whgl 0 - ns 1, 2, 9 we# high to read valid t whqv t avqv + 35 - ns 1, 2, 3, 6, 10 write to asynchronous read specifications we# high to address valid t whav 0 - ns 1, 2, 3, 6, 8 write to synchronous read specifications we# high to clock valid t whch/l 19 - ns 1, 2, 3, 6, 10 we# high to adv# high t whvh 19 - ns we# high to adv# low t whvl 7 - ns write specification with clock active adv# high to we# low t vhwl - 20 ns 1, 2, 3, 11 clock high to we# low t chwl - 20 ns notes: 1. w rite timing characteristics during erase suspend are the same as write-only opera- tions. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. w rite pulse width low ( t wl wh or t eleh) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). thus, t wl wh = t eleh = t wleh = t el wh. 5. w rite pulse width high t whwl or t ehel) is defined from ce# or we# high whichever occurs first) to ce# or we# low whichever occurs last). thus, t whwl = t ehel = t whel = t ehwl). 6. t whvh or t whch/l must be met when transitioning from a write cycle to a synchro- nous burst read. 7. v pp and wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transitioning from a write cycle to an asyn- chronous read. see spec t whch/l and t whvh for synchronous read. 512mb, 1gb, 2gb: p30-65nm ac write specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 85 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
9. when doing a read st a tus operation following any command that alters the status register , t whgl is 20ns. 10. add 10ns if the write operation results in an rcr or block lock status change, for the subsequent read operation to reflect this change. 11. these specs are required only when the device is in a synchronous mode and the clock is active during an address setup phase. 12. this specification must be complied with customers writing timing. the result would be unpredictable if there is any violation to this timing specification. 512mb, 1gb, 2gb: p30-65nm ac write specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 86 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 33: w rite to w rite timing figur e 34: asynchr onous read to w rite timing a t avav ce# oe# wait we# dq rst# t avqv t whax t avwh t elqv t ehqz t glqv t glqx t whdx t elqx t oh q d t dvwh t phqv t ghqz t elwl t gltv t ghtz t wlwh t wheh note: 1. wait de-asserted during asynchronous read and during write. wait high-z during write per oe# deasserted. 512mb, 1gb, 2gb: p30-65nm ac write specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 87 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 35: w rite to asynchr onous read timing 512mb, 1gb, 2gb: p30-65nm ac write specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 88 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 36: synchr onous read to w rite timing a clk adv# ce# oe# we# wait dq t vlch t avch latency count t avvh t avqv t whav t avwh t vlvh t chax t chtv t glqx t glqv t whdx t vlwh t wlwh t elwl t chwl t whwl t chwl t whax t vhwl t vhwl t chqx t elvh t elqv t gltx t vhvl t vhax t elch t ehel t ehtz t wheh t ghqz d d q t chqv t chtx note: 1. wait shown de-asserted and high-z per oe# de-assertion during write operation (rcr10 = 0, wait asserted low). clock is ignored during write operation. 512mb, 1gb, 2gb: p30-65nm ac write specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 89 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figur e 37: w rite to synchr onous read timing a clk adv# ce# we# oe# w ait dq rst# t a vch t vlch t chax t whax t a vwh t a vqv latency count t chtv t g l tx t elch t wheh t whvh t w l wh t glqv t whch/l t wh a v t chqv t elqv t whdx t dvwh t phwl t chqx t chqv t ehel t e l wl t v l vh t vhax d q q note: 1. wait shown de-asserted and high-z per oe# de-assertion during write operation (rcr10 = 0, wait asserted low). 512mb, 1gb, 2gb: p30-65nm ac write specifications pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 90 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program and erase characteristics table 41: program and erase specifications parameter symbol v ppl v pph unit notes min typ max min typ max conventional word programming program time single word t prog/w C 270 456 C 270 456 s 1 buffered programming program time aligned, bp time (32 words) t prog C 310 716 C 310 716 s 1 aligned, bp time (64 words) C 310 900 C 310 900 aligned, bp time (128 words) C 375 1140 C 375 1140 aligned, bp time (256 words) C 505 1690 C 505 1690 one full buf fer , bp time (512 words) C 900 3016 C 900 3016 buffered enhanced factory programming program single byte t befp/b n/a n/a n/a C 0.5 C s 1, 2 befp setup t befp/setup n/a n/a n/a 20 C C 1 erase and suspend erase time 32kb parameter t ers/pb C 0.8 4.0 C 0.8 4.0 s 1 128kb main t ers/mb C 0.8 4.0 C 0.8 4.0 suspend la- tency program suspend t susp/p C 25 30 C 25 30 s erase suspend t susp/e C 25 30 C 25 30 erase-to-suspend t ers/susp C 500 C C 500 C 1, 3 blank check blank check main array block t bc/mb C 3.2 C C 3.2 C ms notes: 1. t ypical values measured at t c = +25c and nominal voltages. performance numbers are valid for all speed versions. excludes system overhead. sampled, but not 100% tested. 2. a veraged over entire device. 3. t ers/susp is the typical time between an initial block erase or erase resume com- mand and the a subsequent erase suspend command. violating the specification re- peatedly during any particular block erase may cause erase failures. 512mb, 1gb, 2gb: p30-65nm program and erase characteristics pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 91 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
revision history rev . b C 12/13 ? o n co v er page , corr ected er ase suspend ( t yp) fr om 30 s to 25 s . ? u pdated par t numbers ? a dded the follo wing par t number disclaimer : "n ot all par t numbers listed her e ar e av ailable for or der ing." ? r evised timings rev . a C 8/13 ? initial micron brand release 8000 s. federal w ay , p .o. box 6, boise, id 83707-0006, t el: 208-368-3900 www .micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron t echnology , inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 512mb, 1gb, 2gb: p30-65nm revision history pdf: 09005aef845667b3 p30_65nm_mlc_512mb-1gb_2gb.pdf - rev. b 12/13 en 92 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.

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